公开(公告)号：US20220264745A1

公开(公告)日：2022-08-18

申请号：US17174904

申请日：2021-02-12

Applicant: RAYTHEON COMPANY

Inventor： Channing Paige Favreau ,  James E. Benedict ,  Mikhail Pevzner ,  Thomas V. Sikina

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/32 ,  H05K1/02

Abstract: A method of fabricating a printed circuit assembly includes providing a flexible-hybrid circuit having a base and at least one side panel. The at least one side panel is hingedly connected to the base. The method further includes disposing a support structure on the flexible-hybrid circuit. The support structure includes a base, which is disposed on the base of the flexible-hybrid circuit, and at least one side that corresponds to the at least one side panel of the flexible-hybrid circuit. The method further includes folding the at least one side panel of the flexible-hybrid circuit so that the at least one side panel is disposed co-planar with the at least one side of the support structure to create a printed circuit assembly.

公开(公告)号：US20210400820A1

公开(公告)日：2021-12-23

申请号：US17465292

申请日：2021-09-02

Applicant: RAYTHEON COMPANY

Inventor： James E. Benedict ,  Gregory G. Beninati ,  Mikhail Pevzner ,  Thomas V. Sikina ,  Andrew R. Southworth

IPC: H05K3/34 ,  H05K3/00

Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.

公开(公告)号：US11171101B2

公开(公告)日：2021-11-09

申请号：US16836470

申请日：2020-03-31

Applicant: RAYTHEON COMPANY

Inventor： James E. Benedict ,  Paul A. Danello ,  Mikhail Pevzner ,  Thomas V. Sikina ,  Andrew R. Southworth

IPC: H01L23/00

Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.

公开(公告)号：US20210144864A1

公开(公告)日：2021-05-13

申请号：US16678188

申请日：2019-11-08

Applicant: RAYTHEON COMPANY

Inventor： Mikhail Pevzner ,  Gregory G. Beninati ,  James E. Benedict ,  Andrew R. Southworth

IPC: H05K3/46

Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.

公开(公告)号：US12249752B2

公开(公告)日：2025-03-11

申请号：US17929374

申请日：2022-09-02

Applicant: Raytheon Company

Inventor： Channing Paige Favreau ,  Mikhail Pevzner ,  Alexander T. Gilbert ,  Thomas V. Sikina

IPC: H01Q1/12 ,  H01Q1/28 ,  H01Q1/48 ,  H01Q9/04

Abstract: A compressible dielectric standoff configured to mount at least one antenna on a ground plane of an antenna assembly includes a ground plane end configured to contact the ground plane and at least one antenna end configured to contact the at least one antenna. The compressible dielectric standoff is movable between a compressed state in which the ground plane end is spaced apart from the at least one antenna end a first distance, and an expanded state in which the ground plane end is spaced apart from the at least one antenna end a second distance. The first distance is smaller than the second distance.

公开(公告)号：US20230209728A1

公开(公告)日：2023-06-29

申请号：US18173390

申请日：2023-02-23

Applicant: RAYTHEON COMPANY

Inventor： Mikhail Pevzner ,  Gregory G. Beninati ,  James E. Benedict ,  Andrew R. Southworth

IPC: H05K3/46

CPC classification number: H05K3/465 ,  H05K3/4679

Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.

公开(公告)号：US20230170599A1

公开(公告)日：2023-06-01

申请号：US17929374

申请日：2022-09-02

Applicant: Raytheon Company

Inventor： Channing Paige Favreau ,  Mikhail Pevzner ,  Alexander T. Gilbert ,  Thomas V. Sikina

IPC: H01Q1/12 ,  H01Q1/48 ,  H01Q1/28 ,  H01Q9/04

CPC classification number: H01Q1/1235 ,  H01Q1/48 ,  H01Q1/28 ,  H01Q9/0407

Abstract: A compressible dielectric standoff configured to mount at least one antenna on a ground plane of an antenna assembly includes a ground plane end configured to contact the ground plane and at least one antenna end configured to contact the at least one antenna. The compressible dielectric standoff is movable between a compressed state in which the ground plane end is spaced apart from the at least one antenna end a first distance, and an expanded state in which the ground plane end is spaced apart from the at least one antenna end a second distance. The first distance is smaller than the second distance.

公开(公告)号：US11606865B2

公开(公告)日：2023-03-14

申请号：US16678188

申请日：2019-11-08

Applicant: RAYTHEON COMPANY

Inventor： Mikhail Pevzner ,  Gregory G. Beninati ,  James E. Benedict ,  Andrew R. Southworth

IPC: H05K3/46

Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.

公开(公告)号：US11317502B2

公开(公告)日：2022-04-26

申请号：US16874794

申请日：2020-05-15

Applicant: Raytheon Company

Inventor： Thomas V. Sikina ,  John P. Haven ,  James E. Benedict ,  William J. Clark ,  Channing P. Favreau ,  Erika Klek ,  Mikhail Pevzner ,  Donald G. Hersey ,  Gregory G. Beninati ,  Thomas J. Tellinghuisen

IPC: H05K1/00 ,  H05K1/02 ,  H01P1/20 ,  H05K7/14

Abstract: Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.

公开(公告)号：US20210360772A1

公开(公告)日：2021-11-18

申请号：US16874794

申请日：2020-05-15

Applicant: Raytheon Company

Inventor： Thomas V. Sikina ,  John P. Haven ,  James E. Benedict ,  William J. Clark ,  Channing P. Favreau ,  Erika Klek ,  Mikhail Pevzner ,  Donald G. Hersey ,  Gregory G. Beninati ,  Thomas J. Tellinghuisen

IPC: H05K1/02 ,  H05K7/14 ,  H01P1/20

Abstract: Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.