公开(公告)号：US09985043B2

公开(公告)日：2018-05-29

申请号：US15498547

申请日：2017-04-27

Applicant: Renesas Electronics Corporation

Inventor： Shibun Tsuda

IPC: H01L21/336 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/792 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7856 ,  H01L29/792

Abstract: An improvement is achieved in the reliability of a semiconductor device. In a memory cell region, a plurality of fins are provided which are portions of a semiconductor substrate extending in an x-direction along a main surface of the semiconductor substrate and spaced apart from each other in a y-direction orthogonal to the x-direction along the main surface of the semiconductor substrate. Between the fins adjacent to each other in the y-direction, a portion of an upper surface of an isolation region is at a position higher than a surface obtained by connecting a position of the upper surface of the isolation region which is in contact with a side wall of one of the fins to a position of the upper surface of the isolation region which is in contact with a side wall of the other fin. In a cross section along the y-direction, the upper surface of the isolation region has a projecting shape.

公开(公告)号：US09780109B2

公开(公告)日：2017-10-03

申请号：US15265473

申请日：2016-09-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke Takeuchi ,  Eiji Tsukuda ,  Kenichiro Sonoda ,  Shibun Tsuda

IPC: H01L31/119 ,  H01L21/00 ,  H01L21/84 ,  H01L27/11573 ,  H01L29/78 ,  H01L27/11565 ,  H01L29/423

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.