公开(公告)号：US20180342526A1

公开(公告)日：2018-11-29

申请号：US15916241

申请日：2018-03-08

Applicant: Renesas Electronics Corporation

Inventor： Shibun Tsuda

IPC: H01L27/1157 ,  H01L21/762

Abstract: A semiconductor device of the present invention includes: an element isolation part which is disposed between fins and whose height is lower than the height of each fin; a memory gate electrode placed over the fins and the element isolation part with a memory gate insulating film having a charge storage part in between; and a control gate electrode disposed in line with the memory gate electrode. The height of the element isolation part below the memory gate electrode is higher than the height of the element isolation part below the control gate electrode. A mismatch between electron injection and hole injection is improved, rewriting operation speed is accelerated, and reliability is enhanced by making the height of the element isolation part below the memory gate electrode higher than the height of the element isolation part below the control gate electrode as mentioned above.

公开(公告)号：US10062706B2

公开(公告)日：2018-08-28

申请号：US15682492

申请日：2017-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke Takeuchi ,  Eiji Tsukuda ,  Kenichiro Sonoda ,  Shibun Tsuda

IPC: H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11565 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/7856 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

公开(公告)号：US12125703B2

公开(公告)日：2024-10-22

申请号：US17697418

申请日：2022-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun Tsuda

IPC: H01L29/76 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/94

CPC classification number: H01L21/0272 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/7624

Abstract: After a plurality of trenches is formed in an SOI substrate, a side surface of the insulating layer is retreated from a side surface of the semiconductor layer and a side surface of the semiconductor substrate. Next, the side surface of the insulating layer is covered with an organic film and also the side surface of the semiconductor layer is exposed from the organic film by performing an anisotropic etching process to the organic film embedded into an inside of each of the plurality of trenches. Next, each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate is approached to the side surface of the insulating layer by performing an isotropic etching process. Further, after the organic film is removed, an oxidation treatment is performed to each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate.

公开(公告)号：US10580785B2

公开(公告)日：2020-03-03

申请号：US15916241

申请日：2018-03-08

Applicant: Renesas Electronics Corporation

Inventor： Shibun Tsuda

IPC: H01L29/78 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/762 ,  H01L29/792 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11536 ,  H01L29/49

Abstract: A semiconductor device of the present invention includes: an element isolation part which is disposed between fins and whose height is lower than the height of each fin; a memory gate electrode placed over the fins and the element isolation part with a memory gate insulating film having a charge storage part in between; and a control gate electrode disposed in line with the memory gate electrode. The height of the element isolation part below the memory gate electrode is higher than the height of the element isolation part below the control gate electrode. A mismatch between electron injection and hole injection is improved, rewriting operation speed is accelerated, and reliability is enhanced by making the height of the element isolation part below the memory gate electrode higher than the height of the element isolation part below the control gate electrode as mentioned above.

公开(公告)号：US10600799B2

公开(公告)日：2020-03-24

申请号：US15366047

申请日：2016-12-01

Applicant: Renesas Electronics Corporation

Inventor： Shibun Tsuda ,  Tomohiro Yamashita

IPC: H01L27/115 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/088 ,  H01L27/11573 ,  H01L21/8234

Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.

公开(公告)号：US10483275B2

公开(公告)日：2019-11-19

申请号：US16243319

申请日：2019-01-09

Applicant: Renesas Electronics Corporation

Inventor： Shibun Tsuda

IPC: H01L21/762 ,  H01L27/11568 ,  H01L27/088 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1157 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film having a first thickness over a main surface of a semiconductor substrate and then forming a second insulating film having a second thickness larger than the first thickness over the first insulating film, sequentially processing the second insulating film, the first insulating film, and the semiconductor substrate to form a plurality of trenches and to form a plurality of projecting portions which include portions of the semiconductor substrate extending in a first direction along the main surface of the semiconductor substrate and are spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate, and depositing a third insulating film over the main surface of the semiconductor substrate such that the third insulating film is embedded in the trenches.

公开(公告)号：US11217605B2

公开(公告)日：2022-01-04

申请号：US17003245

申请日：2020-08-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun Tsuda

IPC: H01L27/12 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L21/84 ,  H01L21/02 ,  H01L21/32 ,  H01L21/8238

Abstract: The first gate insulating film is an insulating film made of silicon oxide, and to which hafnium (Hf) is added without addition of aluminum (Al). Also, the second gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added without addition of hafnium. The third gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added. Further, the fourth gate insulating film is an insulating film made of silicon oxide, and to which hafnium is added. Accordingly, it is possible to reduce the power consumption of the semiconductor device.

公开(公告)号：US11069581B2

公开(公告)日：2021-07-20

申请号：US16719385

申请日：2019-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun Tsuda

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/12

Abstract: The reliability of the semiconductor device is suppressed from deteriorating. A first gate electrode is formed on the semiconductor layer SM located in the SOI region 1A of the substrate 1 having the semiconductor base material SB, the insulating layer BX, and the semiconductor layer SM via the first gate insulating film, a second gate electrode is formed on the semiconductor base material SB located in the first region 1Ba of the bulk region 1B and on which the epitaxial growth treatment is performed via the second gate insulating film, and a third gate electrode is formed on the semiconductor base material SB located in the second region 1Bb of the bulk region 1B and on which the epitaxial growth treatment is not performed via the third gate insulating film.

公开(公告)号：US11101281B2

公开(公告)日：2021-08-24

申请号：US16384444

申请日：2019-04-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun Tsuda

IPC: H01L21/28 ,  H01L27/11565 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: The semiconductor device includes a fin FA selectively protruded from an upper surface of a semiconductor substrate SB, a gate insulating film GF1 formed on an upper surface and a side surface of the fin FA and having an insulating film X1 and a charge storage layer CSL, and a memory gate electrode MG formed on the gate insulating film GF1. Here, the thickness of the charge storage layer CSL on the upper surface of the fin FA is larger than the thickness of the charge storage layer CSL on the side surface of the fin FA.

公开(公告)号：US10211216B2

公开(公告)日：2019-02-19

申请号：US15961334

申请日：2018-04-24

Applicant: Renesas Electronics Corporation

Inventor： Shibun Tsuda

IPC: H01L27/088 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1157 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, a plurality of first projecting portions which include portions of the semiconductor substrate provided in a first region of the semiconductor substrate to extend in a first direction along the main surface of the semiconductor substrate and to be spaced apart from each other in a second direction, orthogonal to the first direction, along the main surface of the semiconductor substrate, a first isolation region provided between the first projecting portions adjacent to each other, and first and second transistors provided in and over an upper part of each of the first projecting portions which is exposed from an upper surface of the first isolation region to be adjacent to each other in the first direction.