公开(公告)号：US09837460B2

公开(公告)日：2017-12-05

申请号：US15363585

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Yosuke Takeuchi ,  Tatsuya Kunikiyo

IPC: H01L27/146 ,  H01L31/11

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14698 ,  H01L31/1105

Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n−-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n−-type semiconductor region, and a p−-type semiconductor region formed between the n−-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n−-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p−-type semiconductor region is lower than a net impurity concentration in the p-type well.

公开(公告)号：US10134796B2

公开(公告)日：2018-11-20

申请号：US15802937

申请日：2017-11-03

Applicant: Renesas Electronics Corporation

Inventor： Yosuke Takeuchi ,  Tatsuya Kunikiyo

IPC: H01L27/146 ,  H01L31/11

Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n−-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n−-type semiconductor region, and a p−-type semiconductor region formed between the n−-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n−-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p−-type semiconductor region is lower than a net impurity concentration in the p-type well.

公开(公告)号：US10062706B2

公开(公告)日：2018-08-28

申请号：US15682492

申请日：2017-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke Takeuchi ,  Eiji Tsukuda ,  Kenichiro Sonoda ,  Shibun Tsuda

IPC: H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11565 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/7856 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

公开(公告)号：US09780109B2

公开(公告)日：2017-10-03

申请号：US15265473

申请日：2016-09-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke Takeuchi ,  Eiji Tsukuda ,  Kenichiro Sonoda ,  Shibun Tsuda

IPC: H01L31/119 ,  H01L21/00 ,  H01L21/84 ,  H01L27/11573 ,  H01L29/78 ,  H01L27/11565 ,  H01L29/423

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.