公开(公告)号：US10062706B2

公开(公告)日：2018-08-28

申请号：US15682492

申请日：2017-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke Takeuchi ,  Eiji Tsukuda ,  Kenichiro Sonoda ,  Shibun Tsuda

IPC: H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11565 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/7856 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

公开(公告)号：US09184264B2

公开(公告)日：2015-11-10

申请号：US14586452

申请日：2014-12-30

Applicant: Renesas Electronics Corporation

Inventor： Eiji Tsukuda ,  Kozo Katayama ,  Kenichiro Sonoda ,  Tatsuya Kunikiyo

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

公开(公告)号：US09780109B2

公开(公告)日：2017-10-03

申请号：US15265473

申请日：2016-09-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke Takeuchi ,  Eiji Tsukuda ,  Kenichiro Sonoda ,  Shibun Tsuda

IPC: H01L31/119 ,  H01L21/00 ,  H01L21/84 ,  H01L27/11573 ,  H01L29/78 ,  H01L27/11565 ,  H01L29/423

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

公开(公告)号：US10438663B2

公开(公告)日：2019-10-08

申请号：US16009535

申请日：2018-06-15

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro Sonoda ,  Eiji Tsukuda ,  Keiichi Maekawa

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06 ,  H01L29/792 ,  G11C16/14 ,  H01L21/84 ,  H01L27/12 ,  G11C16/06

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

公开(公告)号：US10217759B2

公开(公告)日：2019-02-26

申请号：US15669595

申请日：2017-08-04

Applicant: Renesas Electronics Corporation

Inventor： Eiji Tsukuda ,  Kenichiro Sonoda

IPC: H01L27/11568 ,  H01L27/11565 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157

Abstract: To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.

公开(公告)号：US08956941B2

公开(公告)日：2015-02-17

申请号：US14155961

申请日：2014-01-15

Applicant: Renesas Electronics Corporation

Inventor： Eiji Tsukuda ,  Kozo Katayama ,  Kenichiro Sonoda ,  Tatsuya Kunikiyo

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract translation: 提供包括具有更高可靠性的存储单元的半导体器件的制造方法。 形成存储单元形成区域中的第一和第二堆叠结构，以在晶体管形成区域中具有比第三层叠结构更大的高度，然后形成层间绝缘层以覆盖这些堆叠结构，然后进行抛光。

公开(公告)号：US11923296B2

公开(公告)日：2024-03-05

申请号：US17841203

申请日：2022-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naohito Suzumura ,  Kenichiro Sonoda ,  Hideaki Tsuchiya

IPC: H01L23/525

CPC classification number: H01L23/5256

Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

公开(公告)号：US10026481B2

公开(公告)日：2018-07-17

申请号：US15597294

申请日：2017-05-17

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro Sonoda ,  Eiji Tsukuda ,  Keiichi Maekawa

IPC: G11C16/08 ,  G11C16/10 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06 ,  H01L29/792 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.