公开(公告)号：US10379941B2

公开(公告)日：2019-08-13

申请号：US15446501

申请日：2017-03-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukitoshi Tsuboi ,  Hiroyuki Hamasaki

IPC: G06F11/00 ,  G06F11/10

Abstract: The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

公开(公告)号：US10230402B2

公开(公告)日：2019-03-12

申请号：US15925193

申请日：2018-03-19

Applicant: Renesas Electronics Corporation

Inventor： Yukitoshi Tsuboi ,  Hideo Nagano

IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10 ,  H03M13/09 ,  H03M13/13 ,  H03M13/19 ,  H03M13/11 ,  H03M13/15 ,  H03M13/37

Abstract: A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a parity generating circuit which generates a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a parity check circuit which is coupled between the memory and the processor, and which detects a presence or absence of an error of one bit or two bits in the read data and the parity read from the memory, wherein the parity generating circuit generates the parity so that at least one of a first write data bit and a second write data bit included in the write data contributes to generation of at least two parity bits.

公开(公告)号：US10042791B2

公开(公告)日：2018-08-07

申请号：US15588246

申请日：2017-05-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuya Hirade ,  Yukitoshi Tsuboi ,  Ryosuke Okuda

IPC: G06F13/24 ,  G06F11/22

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

公开(公告)号：US09647693B2

公开(公告)日：2017-05-09

申请号：US14590913

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Yukitoshi Tsuboi ,  Hideo Nagano

IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10 ,  H03M13/09 ,  H03M13/13 ,  H03M13/19 ,  H03M13/15 ,  H03M13/37

CPC classification number: H03M13/2927 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1052 ,  H03M13/095 ,  H03M13/11 ,  H03M13/13 ,  H03M13/1575 ,  H03M13/19 ,  H03M13/29 ,  H03M13/3715 ,  H03M13/6575

Abstract: A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.