公开(公告)号：US20220224325A1

公开(公告)日：2022-07-14

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/16

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20210074851A1

公开(公告)日：2021-03-11

申请号：US16868456

申请日：2020-05-06

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Wei Chiu ,  Ta-Yung Yang ,  Wu-Te Weng ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chih-Wen Hsiung ,  Kuo-Chin Chiu ,  Chun-Lung Chang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.

公开(公告)号：US20190302822A1

公开(公告)日：2019-10-03

申请号：US16274162

申请日：2019-02-12

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Yu Chen ,  Tsung-Yi Huang ,  Ting-Wei Liao

IPC: G05F3/22 ,  H03K17/22 ,  H03K19/003 ,  H02H9/04

Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

公开(公告)号：US11876453B2

公开(公告)日：2024-01-16

申请号：US17560761

申请日：2021-12-23

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/38

CPC classification number: H02M3/158 ,  H02M1/385

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

公开(公告)号：US20220238727A1

公开(公告)日：2022-07-28

申请号：US17571401

申请日：2022-01-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/866 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.

公开(公告)号：US10811532B2

公开(公告)日：2020-10-20

申请号：US16352795

申请日：2019-03-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Yu Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.

公开(公告)号：US20190378924A1

公开(公告)日：2019-12-12

申请号：US16352795

申请日：2019-03-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Yu Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.