公开(公告)号：US20170004879A1

公开(公告)日：2017-01-05

申请号：US15206616

申请日：2016-07-11

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Wayne Frederick Ellis

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C5/02 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract translation: 存储器件包括电阻存储器单元阵列，其中每对电阻存储器单元包括与第一电阻存储器元件串联电耦合的第一开关元件和与第二电阻存储元件串联电耦合的第二开关元件。 第一开关元件的源极和第二开关元件的源接收公共源极线信号。

公开(公告)号：US09230641B2

公开(公告)日：2016-01-05

申请号：US14210085

申请日：2014-03-13

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node.

Abstract translation: 存储器件包括电阻存储器单元阵列。 阵列中的每个电阻性存储单元包括第一电阻性存储器元件，第二电阻性存储器元件，其与第一电阻性存储器元件电连接在第一电阻性存储器元件的第一端子与第二电阻性存储器的第一端子之间的公共节点处 元件，以及包括与公共节点电耦合的栅极的晶体管。

公开(公告)号：US20150162382A1

公开(公告)日：2015-06-11

申请号：US14568011

申请日：2014-12-11

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Christophe J. Chevallier ,  Lidia Vereen ,  Philip F.S. Swab ,  Elizabeth Friend ,  Mehmet Gunhan Ertosun

IPC: H01L27/24 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2213/72 ,  G11C2213/78 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146

Abstract: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.

Abstract translation: 存储器件包括电阻存储器单元阵列。 阵列中的每个电阻性存储单元包括第一电阻存储器元件，第二电阻存储元件和两端开关元件。 第一电阻性存储元件在公共节点处电耦合到第二电阻性存储器元件和电连接到开关元件。

公开(公告)号：US09941005B2

公开(公告)日：2018-04-10

申请号：US15338872

申请日：2016-10-31

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

公开(公告)号：US09490009B2

公开(公告)日：2016-11-08

申请号：US14987309

申请日：2016-01-04

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C16/04 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract translation: 存储单元包括第一电阻性存储器元件，在公共节点处与第一电阻式存储器元件电耦合的第二电阻存储元件，以及包括与公共节点电耦合的输入端的开关元件，该开关元件包括驱动器配置 在一个或多个操作期间浮动。

公开(公告)号：US09390798B2

公开(公告)日：2016-07-12

申请号：US14567988

申请日：2014-12-11

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Wayne Frederick Ellis

IPC: G11C13/00 ,  G11C5/06 ,  G11C5/02

CPC classification number: G11C13/004 ,  G11C5/02 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract translation: 存储器件包括电阻存储器单元阵列，其中每对电阻存储器单元包括与第一电阻存储器元件串联电耦合的第一开关元件和与第二电阻存储元件串联电耦合的第二开关元件。 第一开关元件的源极和第二开关元件的源接收公共源极线信号。

公开(公告)号：US09087572B2

公开(公告)日：2015-07-21

申请号：US14091213

申请日：2013-11-26

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Brent Steven Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G11C7/00 ,  G11C15/00 ,  G11C13/00 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C13/0002 ,  G11C15/046

Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

Abstract translation: 内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。 诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。 在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。 匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。 内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。