公开(公告)号：US20250103508A1

公开(公告)日：2025-03-27

申请号：US18812262

申请日：2024-08-22

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Taeksang Song ,  Christopher Haywood

IPC: G06F12/1009 ,  G06F12/02 ,  G06F13/16

Abstract: Described are computational systems in which hosts share pooled memory on the same memory module. A memory buffer with access to the pooled memory manages which regions of the memory are allocated to the different hosts such that memory regions, and thus the data they contain, can be exchanged between hosts. Unidirectional or bidirectional data exchanges between hosts swap regions of equal size so the amount of memory allocated to each host is not changed as a result of the exchange.

公开(公告)号：US12197602B2

公开(公告)日：2025-01-14

申请号：US17968488

申请日：2022-10-18

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson

IPC: G06F12/14 ,  G06F21/57 ,  G06F21/62 ,  G06F11/07 ,  G06F11/14

Abstract: A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor. In response to a failure of the primary processor, the secure processor is to: verify a log retrieval command received via the interface circuitry, wherein the log retrieval command is cryptographically signed; in response to the verification, retrieve crash dump data stored in memory that is accessible by the primary processor; generate a log file that comprises the retrieved crash dump data; and cause the log file to be transmitted to the at least one host system over a sideband link that is coupled externally to the interface circuitry.

公开(公告)号：US20240201894A1

公开(公告)日：2024-06-20

申请号：US18540670

申请日：2023-12-14

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673

Abstract: An apparatus and method for low page overhead recompression. In one embodiment a memory buffer integrated circuit (IC) device is disclosed that includes a first circuit configured to independently compress equally sized portions of a page of data, and a second circuit configured to store the compressed data portions at respective addresses in memory. The memory buffer IC device also includes a third circuit configured to store a page table comprising an entry with information related to the respective memory addresses.

公开(公告)号：US20240143197A1

公开(公告)日：2024-05-02

申请号：US18494641

申请日：2023-10-25

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Michael Alexander Hamburg ,  Helena Handschuh ,  Mark Evan Marson

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0673

Abstract: Technologies for modal encryption are described. One memory buffer device includes a compression block and an in-line memory encryption (IME) block. The compression block can output compressed data. The IME block can encrypt uncompressed data at a first granularity and encrypt the compressed data at a second granularity, wherein the second granularity is larger than the first granularity.

公开(公告)号：US20240012565A1

公开(公告)日：2024-01-11

申请号：US18218831

申请日：2023-07-06

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Craig E. Hampel

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to perform a memory compression operation on first uncompressed data that is stored in a first memory region. Compression circuitry, in response to the at least one command, compresses the first uncompressed data to first compressed data. The first compressed data is transferred to a second memory region.

公开(公告)号：US20230401311A1

公开(公告)日：2023-12-14

申请号：US18202517

申请日：2023-05-26

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Helena Handschuh ,  Michael Alexander Hamburg ,  Mark Evan Marson ,  Michael Raymond Miller

IPC: G06F21/55 ,  G06F11/10

CPC classification number: G06F21/552 ,  G06F11/10

Abstract: Technologies for detecting an error using a message authentication code (MAC) associated with cache line data and differentiating the error as having been caused by an attack on memory or a MAC verification failure caused by an ECC escape. One memory buffer device includes an in-line memory encryption (IME) circuit to generate the MACs and verify the MACs. Upon a MAC verification failure, the memory buffer device can analyze at least one of the historical MAC verification failures or historical ECC-corrected errors over time to determine if the error is caused by an attack on memory.

公开(公告)号：US11657007B2

公开(公告)日：2023-05-23

申请号：US17333420

申请日：2021-05-28

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F13/16 ,  G06F12/02

CPC classification number: G06F13/1668 ,  G06F12/023 ,  G06F2212/1044

Abstract: A multi-path fabric interconnected system with many nodes and many communication paths from a given source node to a given destination node. A memory allocation device on an originating node (local node) requests an allocation of memory from a remote node (i.e., requests a remote allocation). The memory allocation device on the local node selects the remote node based on one or more performance indicators. The local memory allocation device may select the remote node to provide a remote allocation of memory based on one or more of: latency, availability, multi-path bandwidth, data access patterns (both local and remote), fabric congestion, allowed bandwidth limits, maximum latency limits, and, available memory on remote node.

公开(公告)号：US20230138817A1

公开(公告)日：2023-05-04

申请号：US17971964

申请日：2022-10-24

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Evan Lawrence Erickson

IPC: G06F15/78 ,  G06F21/72

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.

公开(公告)号：US20220237113A1

公开(公告)日：2022-07-28

申请号：US17580427

申请日：2022-01-20

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/02 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0871

Abstract: Computing devices, methods, and systems for switch-based free memory tracking in data center environments are disclosed. An exemplary switch integrated circuit (IC), which is used in a switched fabric or a network, can include a processing device and a tracking structure that is distributed with at least a second switch IC. The tracking structure tracks free memory units that are accessible in a first set of nodes by the second switch IC. The processing device receives a request for a number of free memory units. The processing device forwards the request to a node in the first set of nodes that has at least the number of free memory units or forwards the request to the second switch IC that has at least the number of free memory units or responds to the request with a response that indicates that the request could not be fulfilled.

公开(公告)号：US10161788B2

公开(公告)日：2018-12-25

申请号：US14677878

申请日：2015-04-02

Applicant: RAMBUS INC.

Inventor： David Geoffrey Stork ,  Evan Lawrence Erickson ,  Patrick R. Gill ,  James Tringali

IPC: H01J40/14 ,  G01J1/04 ,  H04N5/225 ,  G02B27/00 ,  G02B5/18 ,  G02B27/42 ,  H01L27/146

Abstract: A sensing device projects near-field spatial modulations onto a closely spaced photodetector array. Due to physical properties of the grating, the point-spread response distributes spatial modulations over a relatively large area on the array. The spatial modulations are captured by the array, and photographs and other image information can be extracted from the resultant data. An image-change detector incorporating such a sensing device uses very little power because only a small number of active pixels are required to cover a visual field.