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    REDUCED LATENCY METADATA ENCRYPTION AND DECRYPTION
    1.
    发明申请
    REDUCED LATENCY METADATA ENCRYPTION AND DECRYPTION 有权

    公开(公告)号：US20250047469A1

    公开(公告)日：2025-02-06

    申请号：US18669731

    申请日：2024-05-21

    Applicant: Rambus Inc.

    Inventor： Evan Lawrence Erickson ,  Michael Alexander Hamburg ,  Taeksang Song ,  Wendy Elsasser

    IPC: H04L9/06 ,  G06F21/60

    Abstract: Techniques for providing reduced latency metadata encryption and decryption are described herein. A memory buffer device having a cryptographic circuit to receive a first data and a first metadata associated with the first data. The cryptographic circuit can encrypt or decrypt the first metadata using a first cryptographic algorithm. The cryptographic circuit can encrypt or decrypt the first data using a second cryptographic algorithm. The first data and the first metadata can be stored at a same location, within a memory device, corresponding to a memory address.

    Compression via deallocation
    4.
    发明授权
    Compression via deallocation 有权

    公开(公告)号：US12204446B2

    公开(公告)日：2025-01-21

    申请号：US18140441

    申请日：2023-04-27

    Applicant: Rambus Inc.

    Inventor： Evan Lawrence Erickson ,  Christopher Haywood

    IPC: G06F12/02 ,  G06F12/0891

    Abstract: A buffer/interface device of a memory node reads a block of data (e.g., page). As each unit of data (e.g., cache line sized) of the block is read, it is compared against one or more predefined patterns (e.g., all 0's, all 1's, etc.). If the block (page) is only storing one of the predefined patterns, a flag in the page table entry for the block is set to indicate the block is only storing one of the predefined patterns. The physical memory the block was occupying may then be deallocated so other data may be stored using those physical memory addresses.

    METHOD FOR CACHING AND MIGRATING DE-COMPRESSED PAGE
    6.
    发明公开
    METHOD FOR CACHING AND MIGRATING DE-COMPRESSED PAGE 审中-公开

    公开(公告)号：US20240119001A1

    公开(公告)日：2024-04-11

    申请号：US18377597

    申请日：2023-10-06

    Applicant: Rambus Inc.

    Inventor： Taeksang Song ,  Christopher Haywood ,  Evan Lawrence Erickson

    IPC: G06F12/0802

    CPC classification number: G06F12/0802

    Abstract: Disclosed are techniques for storing data decompressed from the compressed pages of a memory block when servicing data access request from a host device of a memory system to the compressed page data in which the memory block has been compressed into multiple compressed pages. A cache buffer may store the decompressed data for a few compressed pages to save decompression memory space. The memory system may keep track of the number of accesses to the decompressed data in the cache and the number of compressed pages that have been decompressed into the cache to calculate a metric associated with the frequency of access to the compressed pages within the memory block. If the metric does not exceed a threshold, additional compressed pages are decompressed into the cache. Otherwise, all the compressed pages within the memory block are decompressed into a separately allocated memory space to reduce data access latency.

    A FAR MEMORY ALLOCATOR FOR DATA CENTER STRANDED MEMORY
    7.
    发明公开
    A FAR MEMORY ALLOCATOR FOR DATA CENTER STRANDED MEMORY 审中-公开

    公开(公告)号：US20230376412A1

    公开(公告)日：2023-11-23

    申请号：US18030971

    申请日：2021-10-11

    Applicant: RAMBUS INC.

    Inventor： Evan Lawrence Erickson ,  Christopher Haywood

    IPC: G06F12/02

    CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/154

    Abstract: An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory. The processing circuit allocates, on a dynamic basis as a donor, a portion of first local memory of a local server as first far memory for access for a first remote server, or as a requester receives allocation of second far memory from the first remote server or a second remote server for access by the local server. The processing circuit bridges the access by the first remote server to the allocated portion of first local memory as the first far memory, through the fabric addresses and the address translation supported by the first memory, or bridge the access by the local server to the second far memory, through the address translation supported by the first memory, and the fabric addresses.

    REDUNDANT DATA LOG RETRIEVAL IN MULTI-PROCESSOR DEVICE
    8.
    发明公开
    REDUNDANT DATA LOG RETRIEVAL IN MULTI-PROCESSOR DEVICE 审中-公开

    公开(公告)号：US20230161599A1

    公开(公告)日：2023-05-25

    申请号：US17968488

    申请日：2022-10-18

    Applicant: Rambus Inc.

    Inventor： Evan Lawrence Erickson

    IPC: G06F9/4401 ,  H04L67/141

    CPC classification number: G06F9/4406 ,  H04L67/141

    Abstract: A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor. In response to a failure of the primary processor, the secure processor is to: verify a log retrieval command received via the interface circuitry, wherein the log retrieval command is cryptographically signed; in response to the verification, retrieve crash dump data stored in memory that is accessible by the primary processor; generate a log file that comprises the retrieved crash dump data; and cause the log file to be transmitted to the at least one host system over a sideband link that is coupled externally to the interface circuitry.

    MEMORY MODULE WITH MEMORY-OWNERSHIP EXCHANGE
    9.
    发明申请
    MEMORY MODULE WITH MEMORY-OWNERSHIP EXCHANGE 有权

    公开(公告)号：US20250103508A1

    公开(公告)日：2025-03-27

    申请号：US18812262

    申请日：2024-08-22

    Applicant: Rambus Inc.

    Inventor： Evan Lawrence Erickson ,  Taeksang Song ,  Christopher Haywood

    IPC: G06F12/1009 ,  G06F12/02 ,  G06F13/16

    Abstract: Described are computational systems in which hosts share pooled memory on the same memory module. A memory buffer with access to the pooled memory manages which regions of the memory are allocated to the different hosts such that memory regions, and thus the data they contain, can be exchanged between hosts. Unidirectional or bidirectional data exchanges between hosts swap regions of equal size so the amount of memory allocated to each host is not changed as a result of the exchange.

    Redundant data log retrieval in multi-processor device
    10.
    发明授权
    Redundant data log retrieval in multi-processor device 有权

    公开(公告)号：US12197602B2

    公开(公告)日：2025-01-14

    申请号：US17968488

    申请日：2022-10-18

    Applicant: Rambus Inc.

    Inventor： Evan Lawrence Erickson

    IPC: G06F12/14 ,  G06F21/57 ,  G06F21/62 ,  G06F11/07 ,  G06F11/14

    Abstract: A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor. In response to a failure of the primary processor, the secure processor is to: verify a log retrieval command received via the interface circuitry, wherein the log retrieval command is cryptographically signed; in response to the verification, retrieve crash dump data stored in memory that is accessible by the primary processor; generate a log file that comprises the retrieved crash dump data; and cause the log file to be transmitted to the at least one host system over a sideband link that is coupled externally to the interface circuitry.

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