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公开(公告)号:US09569396B2
公开(公告)日:2017-02-14
申请号:US14931652
申请日:2015-11-03
Applicant: Rambus Inc.
Inventor: Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC: G06F3/00 , G06F13/42 , H04L1/00 , H04L1/20 , H04L1/24 , H04L5/14 , G06F13/38 , G06F13/40 , H04L25/02
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
Abstract translation: 一种设备包括耦合到节点的发射器,其中节点将耦合到有线链路。 发射机具有多种操作模式,包括校准模式,其中根据有线链路以预定错误率对应的电压裕度来确定有线链路上的通信数据速率的范围。 通信数据速率的范围包括最大数据速率,其可以是初始数据速率的非整数倍。
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公开(公告)号:US20250054561A1
公开(公告)日:2025-02-13
申请号:US18809250
申请日:2024-08-19
Applicant: Rambus Inc.
Inventor: Yohan U. Frans , Wayne F. Ellis , Akash Bansal
IPC: G11C29/50 , G01R23/02 , G01R23/15 , G01R35/00 , G06F1/08 , G06F1/12 , G06F11/16 , G06F13/16 , G11C7/04 , G11C7/22 , G11C8/18 , G11C29/02 , H03L1/02
Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.
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公开(公告)号:US20230051578A1
公开(公告)日:2023-02-16
申请号:US17751480
申请日:2022-05-23
Applicant: Rambus Inc.
Inventor: Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
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公开(公告)号:US09431131B2
公开(公告)日:2016-08-30
申请号:US14601078
申请日:2015-01-20
Applicant: RAMBUS INC.
Inventor: Yohan U. Frans , Wayne F. Ellis , Akash Bansal
IPC: G06F1/04 , G01R23/00 , G01R23/10 , G01R35/00 , G11C29/50 , G06F13/16 , G01R23/02 , G11C7/22 , G11C29/02 , H03L1/02 , G11C8/18 , G06F11/16 , G06F1/12 , G06F1/08 , G01R23/15 , G11C7/04
CPC classification number: G11C29/50012 , G01R23/02 , G01R23/15 , G01R35/005 , G06F1/08 , G06F1/12 , G06F11/1604 , G06F13/1689 , G11C7/04 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/18 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03L1/02
Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.
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公开(公告)号:US20160035437A1
公开(公告)日:2016-02-04
申请号:US14884601
申请日:2015-10-15
Applicant: RAMBUS INC.
Inventor: Yohan U. Frans , Wayne F. Ellis , Akash Bansal
CPC classification number: G11C29/50012 , G01R23/02 , G01R23/15 , G01R35/005 , G06F1/08 , G06F1/12 , G06F11/1604 , G06F13/1689 , G11C7/04 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/18 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03L1/02
Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.
Abstract translation: 所公开的实施例涉及支持定时漂移校准的存储器系统的组件。 在具体实施例中,该存储器系统包含存储器件(或多个器件),其包括可产生频率的时钟分配电路和振荡器电路,其中频率变化表示时钟分配电路的定时漂移。 存储器件还包括测量电路,其被配置为测量振荡器电路的频率。
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公开(公告)号:US20150131398A1
公开(公告)日:2015-05-14
申请号:US14601078
申请日:2015-01-20
Applicant: RAMBUS INC.
Inventor: Yohan U. Frans , Wayne F. Ellis , Akash Bansal
CPC classification number: G11C29/50012 , G01R23/02 , G01R23/15 , G01R35/005 , G06F1/08 , G06F1/12 , G06F11/1604 , G06F13/1689 , G11C7/04 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/18 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03L1/02
Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.
Abstract translation: 所公开的实施例涉及支持定时漂移校准的存储器系统的组件。 在具体实施例中,该存储器系统包含存储器件(或多个器件),其包括可产生频率的时钟分配电路和振荡器电路,其中频率变化表示时钟分配电路的定时漂移。 存储装置还包括被配置为测量振荡器电路的频率的测量电路。 此外,存储器系统包含存储器控制器,该存储器控制器可向存储器件发送请求以触发存储器件以测量振荡器电路的频率。 存储器控制器还被配置为从存储器件接收测量的频率,并使用测量的频率来确定存储器件中的定时漂移。
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公开(公告)号:US12094553B2
公开(公告)日:2024-09-17
申请号:US17556363
申请日:2021-12-20
Applicant: Rambus Inc.
Inventor: Yohan U. Frans , Wayne F. Ellis , Akash Bansal
IPC: G11C7/22 , G01R23/02 , G06F13/16 , G11C8/18 , G11C29/02 , G11C29/50 , H03L1/02 , G01R23/15 , G01R35/00 , G06F1/08 , G06F1/12 , G06F11/16 , G11C7/04
CPC classification number: G11C29/50012 , G01R23/02 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/18 , G11C29/023 , G11C29/028 , H03L1/02 , G01R23/15 , G01R35/005 , G06F1/08 , G06F1/12 , G06F11/1604 , G11C7/04 , G11C2207/2254
Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.
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公开(公告)号:US11886375B2
公开(公告)日:2024-01-30
申请号:US17751480
申请日:2022-05-23
Applicant: Rambus Inc.
Inventor: Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D30/50
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
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公开(公告)号:US10452601B2
公开(公告)日:2019-10-22
申请号:US15947701
申请日:2018-04-06
Applicant: Rambus Inc.
Inventor: Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
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公开(公告)号:US09940299B2
公开(公告)日:2018-04-10
申请号:US15393234
申请日:2016-12-28
Applicant: Rambus Inc.
Inventor: Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
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