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11.发明授权
公开(公告)号：US6049254A
公开(公告)日：2000-04-11
申请号：US951650
申请日：1997-10-16
申请人： David J. Knapp , David S. Trager , Tony Susanto , Larry L. Harris
发明人： David J. Knapp , David S. Trager , Tony Susanto , Larry L. Harris
CPC分类号： H03L7/197
摘要： An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another. By modifying the frequency division factor, the PLL can dynamically lock upon a changed input signal frequency without varying the clocking signal output from the PLL. Thus, the PLL can accommodate various input signal frequencies yet maintain a relatively fixed clocking signal to be forwarded as a timing reference to a digital processor.
摘要翻译： 提供了一种用于自动和动态地调整位于锁相环（PLL）的反馈环路中的时钟分频器的分频因子的装置。 基于转发到PLL的输入信号频率的变化来修改分频因子。 如果输入信号频率增加，则与作为编码数字信号变化的压控振荡器记录的输入相耦合的判定电路。 该信号将相应地根据当前分频因子以及当前输入信号频率来修改当前的分频因子。 决定电路可以被建模为A / D转换器，放置在判决电路和时钟分频器之间的控制单元可以被建模为状态图。 状态图的每个状态表示分频因子或该分割因子的变化，其中编码的数字信号指示从一个状态到另一个状态的可能的改变。 通过修改分频因子，PLL可以动态地锁定改变的输入信号频率，而不改变从PLL输出的时钟信号。 因此，PLL可以适应各种输入信号频率，同时维持相对固定的时钟信号作为定时参考被转发到数字处理器。
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12.发明授权公开(公告)号：US09041452B2
公开(公告)日：2015-05-26
申请号：US12694630
申请日：2010-01-27
摘要： A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.
摘要翻译： 电路包括电源端子和时钟解析电路，其被配置为产生具有公共时钟周期和不同相位的多个时钟信号。 电路还包括耦合到时钟解析电路和电源端的多个数字电路。 每个数字电路包括用于接收数据和用于处理数据的逻辑的输入。 每个数字电路响应于与多个时钟信号的相应时钟信号相关联的相位，以从调节电源端子抽取电流来处理数据以产生数据输出。 另外，电路包括耦合到多个数字电路中的每一个并被配置为控制多个数字电路中的每一个的数据输出的输出定时管理电路，以防止在一个或多个目的地电路处的定时违反。
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13.发明申请CIRCUIT AND METHOD OF CLOCKING MULITIPLE DIGITAL CIRCUITS IN MULTIPLE PHASES 有权在多个相位中定时切换多个数字电路的电路和方法公开(公告)号：US20110181325A1
公开(公告)日：2011-07-28
申请号：US12694630
申请日：2010-01-27
IPC分类号： H03L7/00
摘要： A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.
摘要翻译： 电路包括电源端子和时钟解析电路，其被配置为产生具有公共时钟周期和不同相位的多个时钟信号。 电路还包括耦合到时钟解析电路和电源端的多个数字电路。 每个数字电路包括用于接收数据和用于处理数据的逻辑的输入。 每个数字电路响应于与多个时钟信号的相应时钟信号相关联的相位，以从调节电源端子抽取电流来处理数据以产生数据输出。 另外，电路包括耦合到多个数字电路中的每一个并被配置为控制多个数字电路中的每一个的数据输出的输出定时管理电路，以防止在一个或多个目的地电路处的定时违反。
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14.发明授权Direct digital frequency synthesizer with phase error correction, method therefor, and receiver using same 失效具有相位误差校正的直接数字频率合成器，其方法和使用其的接收机公开(公告)号：US07889812B2
公开(公告)日：2011-02-15
申请号：US11442195
申请日：2006-05-26
申请人： David S. Trager , Mitchell Reid
发明人： David S. Trager , Mitchell Reid
CPC分类号： G06F1/0353 , G06F1/0335 , G06F1/0342
摘要： A receiver (1000) includes a direct digital frequency synthesizer (DDFS) (700) and first (1040) and second (1042) mixers. The DDFS (700) has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer (1040) has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer (1042) has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS (700) may be implemented using first (702) and second (704) memories storing portions of a sinusoidal waveform and extra memories (706, 708) supporting the phase offset.
摘要翻译： 接收器（1000）包括直接数字频率合成器（DDFS）（700）和第一（1040）和第二（1042）混频器。 DDFS（700）具有用于提供第一本地振荡器信号的第一输出和用于提供与第一本地振荡器信号的正交关系偏移相位偏移的第二本地振荡器信号的第二输出。 第一混频器（1040）具有用于接收射频（RF）信号的第一输入端，用于接收第一本机振荡器信号的第二输入端和用于提供另一频率的同相信号的输出端。 第二混频器（1042）具有用于接收RF信号的第一输入端，用于接收第二本机振荡器信号的第二输入端和用于以另一频率提供正交信号的输出端。 DDFS（700）可以使用存储正弦波形的部分的第一（702）和第二（704）存储器以及支持相位偏移的额外存储器（706,708）来实现。
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15.发明授权Phase-locked loop with protected output during instances when the phase-locked loop is unlocked 失效在锁定环解锁的实例期间，具有受保护输出的锁相环
公开(公告)号：US6005904A
公开(公告)日：1999-12-21
申请号：US951796
申请日：1997-10-16
申请人： David J. Knapp , Tony Susanto , David S. Trager
发明人： David J. Knapp , Tony Susanto , David S. Trager
CPC分类号： H03L7/095 , H03L7/06 , H03L7/18 , H04L7/0083 , H04L7/04 , Y10S331/02
摘要： A circuit is provided for controlling or regulating a phase-locked loop (PLL) output during times when the PLL is unlocked. Noise or corruption on the input signal of the PLL may cause the PLL output frequency to suddenly rise to match the input signal frequency. In many instances, the noise or corruption cannot be filtered by the low pass filter within the PLL. A detection circuit is coupled to receive the input signal, and discern times in which non-filterable noise occurs. The detection circuit may include a decoder which decodes, e.g., error correction coding within the input signal data stream to indicate possible instances in which the PLL will unlock. Once the detection circuit indicates an unlock condition and forwards an unlock selection signal to a multiplexer, the multiplexer chooses a frequency divided clocking signal rather than the PLL output clocking signal. The frequency divided clocking signal transitions at a rate acceptable to a digital processor, while the PLL output clocking signal during an unlock state is not acceptable. Thus, the digital processor can maintain its operating state during times when the PLL clocking signal exceeds the processor maximum operation frequency.
摘要翻译： 提供一个电路，用于在PLL被解锁时控制或调节锁相环（PLL）输出。 PLL输入信号的噪声或损坏可能导致PLL输出频率突然上升，以匹配输入信号频率。 在许多情况下，PLL内的低通滤波器不能滤除噪声或损坏。 耦合检测电路以接收输入信号，并且辨别发生不可过滤噪声的时间。 检测电路可以包括解码器，其解码例如在输入信号数据流内的纠错编码，以指示PLL将解锁的可能情况。 一旦检测电路指示解锁状态并将解锁选择信号转发到复用器，则多路复用器选择分频时钟信号而不是PLL输出时钟信号。 分频时钟信号以数字处理器可接受的速率转换，而解锁状态期间的PLL输出时钟信号是不可接受的。 因此，当PLL时钟信号超过处理器最大工作频率时，数字处理器可以保持其工作状态。
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公开(公告)号：US5835390A
公开(公告)日：1998-11-10
申请号：US580272
申请日：1995-12-27
申请人： David S. Trager
发明人： David S. Trager
CPC分类号： H03H17/0671 , H03H17/0664
摘要： A digital filter is provided for achieving substantial attenuation of aliasing or imaging bands of a signal to be filtered. The digital filter employs a comb filter technique, wherein the comb filter can perform decimation or interpolation, depending upon its application. The comb filter is a multi-stage element, having more than one stage, and having an overall word length, W.sub.L, optimally reduced. The total number of terms within the cumulative set of stages is also optimally reduced. The comb decimation or interpolation filter architecture is therefore of minimum size if employed in hardware, or utilizes minimal operations if employed in software. A filter element within the comb decimation or interpolation filter includes a z-transform C.sub.K (Z) term. The filter element can be reduced to a simple z-transform 1+z.sup.-1 term if the stage of interest includes a decimate-by-two or interpolate-by-two rate change switch.
摘要翻译： 提供数字滤波器用于实现待滤波信号的混叠或成像频带的实质衰减。 数字滤波器采用梳状滤波器技术，其中梳状滤波器可以根据其应用执行抽取或插值。 梳状滤波器是具有多于一个级的多级元件，并且具有最终减小的总字长WL。 累积一组阶段内的总数也最大程度地减少。 因此，梳状抽取或内插滤波器架构在硬件中使用最小尺寸，或者如果在软件中使用，则采用最小的操作。 梳状抽取或插值滤波器内的滤波器元件包括z变换CK（Z）项。 如果感兴趣的阶段包括二进制或二进制速率改变开关，则可以将滤波器元件简化为简单的z变换1 + z-1项。
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公开(公告)号：US5592403A
公开(公告)日：1997-01-07
申请号：US29870
申请日：1993-03-11
申请人： David S. Trager , Akhtar Ali , Frederick J. Highton , Kun Lin
发明人： David S. Trager , Akhtar Ali , Frederick J. Highton , Kun Lin
CPC分类号： H03H17/0628 , H03H17/0223
摘要： A digital signal processor (DSP) circuit is configured to recursively retrieve and process pairs of data points in a symmetric digital filter. The data points are retrieved from an external source (e.g., compact disk) at a first frequency, and processed within the DSP at a second frequency. The DSP employs a floating pointer scheme, which effectively functions a buffer to thereby compensate for jitter or drift between the first and second frequencies.
摘要翻译： 数字信号处理器（DSP）电路被配置为递归地检索和处理对称数字滤波器中的数据点对。 以第一频率从外部源（例如，光盘）检索数据点，并在DSP内以第二频率进行处理。 DSP采用浮动指针方案，其有效地起缓冲器的作用，从而补偿第一和第二频率之间的抖动或漂移。
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