公开(公告)号：US09564540B2

公开(公告)日：2017-02-07

申请号：US14803037

申请日：2015-07-18

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Uozaki ,  Yasuhiro Takeda ,  Keiichi Maekawa ,  Takumi Hasegawa ,  Kota Funayama ,  Yoshiki Maruyama ,  Kazutoshi Shiba ,  Shuichi Kudo

IPC: H01L21/3205 ,  H01L29/788 ,  H01L27/11 ,  H01L29/40 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L29/788 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/792

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract translation: 本发明的目的是通过在同一基板上形成非易失性存储器和MOSFETS来防止栅极电极中的晶粒尺寸的增加来提供具有改善的可靠性的半导体器件。 可以通过分别从相同层的膜形成非易失性存储器的控制栅电极和其它MOSFET的栅电极并且从两个多晶硅的堆叠中配置每个控制栅电极和栅电极来实现该目的 电影层。

公开(公告)号：US20140353740A1

公开(公告)日：2014-12-04

申请号：US14283245

申请日：2014-05-21

Applicant: Renesas Electronics Corporation

Inventor： Akio Nishida ,  Kota Funayama

IPC: H01L27/115 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823864 ,  H01L27/11573 ,  H01L27/1207 ,  H01L29/66833

Abstract: Improvements are achieved in the characteristics of a semiconductor device having a nonvolatile memory (MONOS). In a SOI substrate having a supporting substrate, an insulating layer formed thereover, and a silicon layer formed thereover, the MONOS is formed. The MONOS has a control gate electrode and a memory gate electrode formed so as to be adjacent to the control gate electrode above the semiconductor layer. The MONOS also has a first impurity region formed in the supporting substrate under the control gate electrode and a second impurity region formed in the supporting substrate under the memory gate electrode and having an effective carrier concentration lower than that of the first impurity region. By thus providing the first and second impurity regions for adjusting the respective thresholds of the control transistor and the memory transistor, variations in the thresholds of the individual transistors are reduced to reduce GiDL.

Abstract translation: 具有非易失性存储器（MONOS）的半导体器件的特性得到改善。 在具有支撑基板的SOI基板中，形成有绝缘层，形成有硅层，形成MONOS。 MONOS具有形成为与半导体层上方的控制栅电极相邻的控制栅电极和存储栅电极。 MONOS还具有形成在支撑衬底下的第一杂质区域，在控制栅电极下方形成第二杂质区域，以及形成在存储栅电极下方的支撑衬底中并具有比第一杂质区域低的有效载流子浓度的第二杂质区域。 通过提供用于调节控制晶体管和存储晶体管的相应阈值的第一和第二杂质区域，各个晶体管的阈值的变化被减小以减少GiDL。