公开(公告)号：US20240162353A1

公开(公告)日：2024-05-16

申请号：US18486626

申请日：2023-10-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/861 ,  H01L27/06 ,  H01L29/32 ,  H01L29/739

CPC classification number: H01L29/8613 ,  H01L27/0664 ,  H01L29/32 ,  H01L29/7397

Abstract: A semiconductor device according to the present disclosure includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, and a diode formed in the semiconductor substrate. The diode includes a drift layer of a first conductivity type on a side provided with the first surface, an anode layer of a second conductivity type opposite in conductivity type to the first conductivity type on the drift layer, and a trench. A bottom surface of the anode layer is located in a region deeper than a bottom surface of the trench with reference to the first surface.

公开(公告)号：US20180277668A1

公开(公告)日：2018-09-27

申请号：US15992405

申请日：2018-05-30

Applicant: Renesas Electronics Corporation

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/40 ,  H02M7/537 ,  H01L29/10 ,  H01L29/06 ,  H01L21/761

CPC classification number: H01L29/7397 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66348 ,  H02M7/537 ,  H05K999/99

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

公开(公告)号：US20180248492A1

公开(公告)日：2018-08-30

申请号：US15965178

申请日：2018-04-27

Applicant: Renesas Electronics Corporation

Inventor： Daisuke KONDO ,  Koji TATENO ,  Chang LIU ,  Nao NAGATA

IPC: H02M5/458 ,  H01L29/00 ,  H02M1/08 ,  H03K17/12 ,  H03K17/567 ,  H03K17/61 ,  H03K17/691 ,  H03K17/795

CPC classification number: H02M5/458 ,  H01L29/00 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/7396 ,  H01L29/7397 ,  H02M1/08 ,  H03K17/127 ,  H03K17/168 ,  H03K17/567 ,  H03K17/61 ,  H03K17/691 ,  H03K17/7955 ,  H03K2217/0081

Abstract: A power conversion device includes a high-side transistor including an IGBT, a low-side transistor including an IGBT, and having a collector coupled to an emitter of the high-side transistor, a high-side driver configured to drive the high-side transistor; and a low-side driver configured to drive the low-side transistor, wherein each of the high-side transistor and the low-side transistor includes a first trench gate electrode arranged in an active cell region, and electrically connected to a gate, and a second trench gate electrode and a third trench gate electrode, each of which is arranged at intervals on both sides of the first trench gate electrode, and electrically connected to the emitter in the active cell region. The high-side driver includes a first pull-up transistor configured to apply a first voltage as a positive voltage to the gate, based on the emitter of the high-side transistor and a first pull-down transistor.

公开(公告)号：US20180012984A1

公开(公告)日：2018-01-11

申请号：US15715087

申请日：2017-09-25

Applicant: Renesas Electronics Corporation

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H03K17/12

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66348 ,  H03K17/127

Abstract: A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a third trench gate electrode and a fourth trench gate electrode which are electrically connected to an emitter electrode. A plurality of p+ type semiconductor regions are formed in a part of a semiconductor layer between the first trench gate electrode and the second trench gate electrode. The plurality of p+ type semiconductor regions are arranged to be spaced apart from each other along an extending direction of the first trench gate electrode when seen in a plan view.

公开(公告)号：US20230155013A1

公开(公告)日：2023-05-18

申请号：US17529863

申请日：2021-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L29/7396 ,  H01L27/0635 ,  H01L28/20

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of IGBTs (Insulated Gate Bipolar Transistors) formed on the semiconductor substrate), a gate electrode, a plurality of gate wires coupled to the gates of the IGBTs, and a gate resistor coupled to the gate electrode and the plurality of gate wires, wherein the gate resistor comprises a resistive element, a first contact that couples the gate electrode and the resistive element, and a plurality of second contacts each of which corresponds to each of the plurality of gate wires and couples to the resistive element and the corresponding gate wire, respectively, and wherein each of the plurality of second contacts is formed at a different distance from the first contact.

公开(公告)号：US20220336447A1

公开(公告)日：2022-10-20

申请号：US17231666

申请日：2021-04-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L27/07 ,  H01L29/739

Abstract: A semiconductor device includes a semiconductor substrate having first and second surfaces, an insulated gate bipolar transistor (IGBT) and a diode formed on the semiconductor substrate, wherein the diode comprises a drift layer of a first conductivity type formed so as to have a first region on the first surface of the semiconductor substrate, a first body layer of a second conductivity type formed so as to have a second region adjacent to the first region at an upper portion of the drift layer, a first floating layer of the second conductivity type formed so as to have a third region adjacent to the first region at an upper portion of the drift layer, a first trench electrode formed in a region adjacent to the first floating layer at an upper portion of the drift layer, and a first control gate formed on top of the first region.

公开(公告)号：US20200212209A1

公开(公告)日：2020-07-02

申请号：US16702188

申请日：2019-12-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/49

Abstract: A semiconductor device having an IE-type IGBT structure is disclosed. Concretely, the semiconductor device comprises a stripe-shaped trench gate, a stripe-shaped trench emitter arranged to face the trench gate, an N-type emitter layer and a P-type base layer surrounded by the trench gate and the trench emitter, and a P-type base contact layer arranged on one side of the trench emitter, formed in a semiconductor substrate. The p-type base contact layer, the emitter layer, and the trench emitter are commonly connected with an emitter electrodes, and the trench emitter is formed deeper than the trench gate in a thickness direction of the semiconductor substrate.

公开(公告)号：US20200185500A1

公开(公告)日：2020-06-11

申请号：US16655869

申请日：2019-10-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L21/765

Abstract: A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.

公开(公告)号：US20200066888A1

公开(公告)日：2020-02-27

申请号：US16673425

申请日：2019-11-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.

公开(公告)号：US20190181255A1

公开(公告)日：2019-06-13

申请号：US16175386

申请日：2018-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.