公开(公告)号：US10006955B2

公开(公告)日：2018-06-26

申请号：US15402660

申请日：2017-01-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki Kurooka ,  Yasuo Morimoto ,  Yoshihiro Funato

IPC: G01R31/00 ,  G01R31/02 ,  G01D5/12 ,  H02H7/08 ,  H02P6/12 ,  H03F3/45 ,  H03K3/017

CPC classification number: G01R31/025 ,  G01D5/12 ,  G01D5/24466 ,  H02H7/0833 ,  H02P6/12 ,  H02P6/16 ,  H03F3/45071 ,  H03F3/45475 ,  H03F2200/129 ,  H03F2200/231 ,  H03F2200/234 ,  H03F2200/261 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45171 ,  H03F2203/45528 ,  H03K3/017

Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.

公开(公告)号：US09349727B2

公开(公告)日：2016-05-24

申请号：US14598127

申请日：2015-01-15

Applicant: Renesas Electronics Corporation

Inventor： Kazuaki Deguchi ,  Yasuo Morimoto ,  Masao Ito

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823425 ,  H01L27/0207 ,  H01L29/7846

Abstract: In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.

Abstract translation: 在半导体器件中，有源区包括：施加预定电压的第一杂质区; 形成绝缘栅场效应晶体管的一对导电电极的第二和第三杂质区; 以及设置在第一和第二杂质区域之间的至少一个杂质区域。 将引起第二和第三杂质区之间导电的电压施加到设置在第二和第三杂质区之间的栅电极。 设置在第一和第二杂质区域之间的所有栅极电极被配置为恒定地电连接到第一杂质区域。 设置在第一和第二杂质区域之间的所有杂质区域与第一和第二杂质区域电隔离并保持在浮置状态。