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公开(公告)号：US10145887B2
公开(公告)日：2018-12-04
申请号：US15987572
申请日：2018-05-23
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuaki Kurooka , Yasuo Morimoto , Yoshihiro Funato
Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.
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公开(公告)号：US20150123207A1
公开(公告)日：2015-05-07
申请号：US14598127
申请日：2015-01-15
Applicant: Renesas Electronics Corporation
Inventor： Kazuaki Deguchi , Yasuo Morimoto , Masao Ito
IPC: H01L27/088
CPC classification number: H01L27/088 , H01L21/823425 , H01L27/0207 , H01L29/7846
Abstract: In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.
Abstract translation: 在半导体器件中，有源区包括：施加预定电压的第一杂质区; 形成绝缘栅场效应晶体管的一对导电电极的第二和第三杂质区; 以及设置在第一和第二杂质区域之间的至少一个杂质区域。 将引起第二和第三杂质区之间导电的电压施加到设置在第二和第三杂质区之间的栅电极。 设置在第一和第二杂质区域之间的所有栅极电极被配置为恒定地电连接到第一杂质区域。 设置在第一和第二杂质区域之间的所有杂质区域与第一和第二杂质区域电隔离并保持在浮置状态。
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公开(公告)号：US09843340B2
公开(公告)日：2017-12-12
申请号：US15390606
申请日：2016-12-26
Applicant: Renesas Electronics Corporation
Inventor： Yoshihiro Funato , Yasuo Morimoto
CPC classification number: H03M1/466 , H03M1/06 , H03M1/0695 , H03M1/468
Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
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公开(公告)号：US09698804B1
公开(公告)日：2017-07-04
申请号：US15371101
申请日：2016-12-06
Applicant: Renesas Electronics Corporation
Inventor： Yoshihiro Funato , Yasuo Morimoto , Kazuaki Kurooka
CPC classification number: H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
Abstract: During a period of calibration of the ADC, the effect of unexpected external noise can be excluded.Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.
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公开(公告)号：US10075177B2
公开(公告)日：2018-09-11
申请号：US15797150
申请日：2017-10-30
Applicant: Renesas Electronics Corporation
Inventor： Yoshihiro Funato , Yasuo Morimoto
CPC classification number: H03M1/466 , H03M1/06 , H03M1/0695 , H03M1/468
Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
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Patent Agency Ranking
公开(公告)号：US20180234102A1
公开(公告)日：2018-08-16
申请号：US15952588
申请日：2018-04-13
Applicant: Renesas Electronics Corporation
Inventor： Yoshihiro Funato , Yasuo Morimoto , Kazuaki Kurooka
CPC classification number: H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
Abstract: An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.
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公开(公告)号：US09960779B2
公开(公告)日：2018-05-01
申请号：US15799034
申请日：2017-10-31
Applicant: Renesas Electronics Corporation
Inventor： Yoshihiro Funato , Yasuo Morimoto , Kazuaki Kurooka
CPC classification number: H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
Abstract: An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.
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公开(公告)号：US09838027B2
公开(公告)日：2017-12-05
申请号：US15615719
申请日：2017-06-06
Applicant: Renesas Electronics Corporation
Inventor： Yoshihiro Funato , Yasuo Morimoto , Kazuaki Kurooka
CPC classification number: H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
Abstract: An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n−1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n−1)-th.
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公开(公告)号：US09166612B2
公开(公告)日：2015-10-20
申请号：US14336073
申请日：2014-07-21
Applicant: Renesas Electronics Corporation
Inventor： Masaki Fujiwara , Yasuo Morimoto , Takashi Matsumoto
CPC classification number: H03M1/125 , H03K5/133 , H03K2005/00065 , H03M1/12 , H03M1/38 , H03M1/46 , H03M1/462 , H03M1/468
Abstract: To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.
Abstract translation: 提供能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号来完成该半导体器件，当该周期从比较期间过渡到...时，检测信号及其延迟信号是否被输出 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。
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公开(公告)号：US10128861B2
公开(公告)日：2018-11-13
申请号：US15952588
申请日：2018-04-13
Applicant: Renesas Electronics Corporation
Inventor： Yoshihiro Funato , Yasuo Morimoto , Kazuaki Kurooka
Abstract: An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.
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