公开(公告)号：US06920075B2

公开(公告)日：2005-07-19

申请号：US10450803

申请日：2001-12-14

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/062 ,  G11C7/1006

Abstract: The invention concerns an amplifier (1), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.

Abstract translation: 本发明涉及一种能够被激活信号控制的放大器（1），用于读取交叉开关网络的存储单元，其包括针对每列的直接位线（BLdi）和参考位线（BLri），放大器 对于两列是共同的，并且产生在所述两列中读取的单元的状态的OR-Exclusive类型组合。

公开(公告)号：US20050013163A1

公开(公告)日：2005-01-20

申请号：US10829877

申请日：2004-04-22

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C11/404 ,  G11C16/04 ,  G11C16/28 ,  H01L20060101 ,  H01L27/108

CPC classification number: G11C16/28 ,  G11C11/404 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

Abstract translation: 这里描述和说明了许多发明。 在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。 在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。 也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。 这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“1”）。 可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。 也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

公开(公告)号：US06535987B1

公开(公告)日：2003-03-18

申请号：US09364151

申请日：1999-07-30

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G06F104

CPC classification number: H04L25/0272 ,  H04L25/029 ,  H04L25/0292 ,  H04L25/08

Abstract: The present invention relates to an amplifier having a fan-out which varies according to the time spent between an edge of a propagation signal and an edge of a logic input signal, the amplifier including several identical blocks, each block having an output stage connected between a data input and a data output, the data input and output being respectively connected to the data inputs and outputs of the other blocks; a delay element, the delay elements of all blocks being connected in series, the delay element of the first block receiving the synchronization signal; an edge detector, the input of which is connected to the input of the output stage; and means for inhibiting the propagation of the synchronization signal through the delay element when the signal generated by the edge detector of the preceding block is active and for activating the output stage and the edge detector when the signal generated by the delay element of the preceding block is active.

Abstract translation: 本发明涉及一种放大器，其具有根据在传播信号的边缘和逻辑输入信号的边缘之间消耗的时间而变化的扇出，放大器包括几个相同的块，每个块的输出级连接在 数据输入和数据输出，数据输入和输出分别连接到其他块的数据输入和输出; 延迟元件，所有块的延迟元件串联连接，第一块的延迟元件接收同步信号; 边缘检测器，其输入端连接到输出级的输入端; 以及用于当由前一块的边缘检测器产生的信号有效时禁止同步信号通过延迟元件传播的装置，并且用于当由前一个块的延迟元件产生的信号激活时输出级和边缘检测器 活跃。

公开(公告)号：US06489810B2

公开(公告)日：2002-12-03

申请号：US09891964

申请日：2001-06-26

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: H03K19007

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract translation: 一种具有数字输出的电子电路，包括闩锁（1），控制组件（2），可吹塑组件（3），连接到公共点（14）的第一输入的逻辑门（4））的自动稳定组件， 在自动稳定组件（1）和可吹塑组件（3）之间，以及连接到电子电路的控制输入（20）的第二输入。 断路器（5）由逻辑门（4）的输出控制并且布置在自动稳定组件（1）和地之间，以及相关联的过程。

公开(公告)号：US06373741B2

公开(公告)日：2002-04-16

申请号：US09396617

申请日：1999-09-15

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C506

CPC classification number: G11C11/4096 ,  G11C5/025 ,  G11C7/10

Abstract: An integrated circuit memory including an array of memory cells divided into several sections, and several rows of column decoding amplifiers, the respective outputs of which are interconnected, by column, by means of a decoded bit line, each decoded bit line including two perpendicular sections, one of which is in the row direction to directly connect each decoded bit line to an input of an input-output stage of the memory arranged at one end of the rows.

Abstract translation: 包括被分成几个部分的存储器单元的阵列的集成电路存储器和通过解码的位线通过列互连的多行列解码放大器，每个解码的位线包括两个垂直部分 其中一个在行方向上将每个解码的位线直接连接到布置在行的一端的存储器的输入 - 输出级的输入。

公开(公告)号：US08664712B2

公开(公告)日：2014-03-04

申请号：US12946135

申请日：2010-11-15

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/12 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.

Abstract translation: 本发明涉及一种闪存单元，其具有在绝缘体上绝缘体（SOI）衬底上具有浮置栅极的FET晶体管，该半导体材料由通过绝缘掩埋氧化物（BOX）层从基底衬底分离的半导体材料薄膜构成， 晶体管在薄膜中具有通道，具有两个控制栅极，位于浮置栅极上方的前控制栅极，并通过栅极间电介质与栅极间绝缘体分离，以及位于绝缘子下方的基底衬底内的反控制栅极 （BOX）层，并且仅通过绝缘（BOX）层与沟道分离。 两个控制门被设计成组合使用以执行单元编程操作。 本发明还涉及由根据本发明的第一方面的多个存储单元组成的存储器阵列，其可以是行和列的阵列，以及制造这种存储单元和存储器阵列的方法。

公开(公告)号：US08358552B2

公开(公告)日：2013-01-22

申请号：US12789100

申请日：2010-05-27

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: G11C7/00

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2211/4016

Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

Abstract translation: 一种用于存储器的一系列单元的读出放大器，包括一个写入级，它包括一个CMOS反相器，其输入直接或间接地连接到读出放大器的输入端，并且其输出端连接到输出端 所述读出放大器旨在连接到寻址该串联的单元的本地位线;以及读取级，其包括检测晶体管，其栅极连接到反相器的输出端，其漏极连接到 输入变频器。

公开(公告)号：US20120243360A1

公开(公告)日：2012-09-27

申请号：US13422697

申请日：2012-03-16

Applicant: Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

Inventor： Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

IPC: G11C7/06 ,  G11C8/10

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/4097

Abstract: A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.

Abstract translation: 具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。 每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。 这导致互连空间与位线平行。 此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

公开(公告)号：US08266494B2

公开(公告)日：2012-09-11

申请号：US12140643

申请日：2008-06-17

Applicant: Richard Ferrant ,  Cédric Maufront

Inventor： Richard Ferrant ,  Cédric Maufront

IPC: H03M13/00

CPC classification number: H04L25/14 ,  H04L1/0043 ,  H04L2001/0094

Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

Abstract translation: 包括串联耦合的多个逻辑块的数据总线，每个逻辑块包括用于缓冲经由数据总线传输的至少一个数据位的至少一个缓冲器，以及至少一个逻辑块，还包括与该数据总线并联耦合的电路 至少一个缓冲器，并被布置成确定与所述至少一个数据位相关联的纠错码的第一位。

公开(公告)号：US20110222361A1

公开(公告)日：2011-09-15

申请号：US12789100

申请日：2010-05-27

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: G11C7/06

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2211/4016

Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

Abstract translation: 一种用于存储器的一系列单元的读出放大器，包括一个写入级，它包括一个CMOS反相器，其输入直接或间接地连接到读出放大器的输入端，并且其输出端连接到输出端 所述读出放大器旨在连接到寻址该串联的单元的本地位线;以及读取级，其包括检测晶体管，其栅极连接到反相器的输出端，其漏极连接到 输入变频器。