公开(公告)号：US5909126A

公开(公告)日：1999-06-01

申请号：US672676

申请日：1996-06-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/04 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  H03K19/04

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。

公开(公告)号：US5977793A

公开(公告)日：1999-11-02

申请号：US855192

申请日：1997-05-13

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H01L21/82 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/1778

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

公开(公告)号：US06215326B1

公开(公告)日：2001-04-10

申请号：US09266235

申请日：1999-03-10

申请人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC分类号： H03K19177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

摘要翻译： 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源 装置。

公开(公告)号：US06879183B2

公开(公告)日：2005-04-12

申请号：US10260712

申请日：2002-09-27

申请人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

摘要翻译： 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源 装置。

公开(公告)号：US06335634B1

公开(公告)日：2002-01-01

申请号：US09577297

申请日：2000-05-22

申请人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

发明人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

IPC分类号： G06F738

CPC分类号： H03K19/17736 ,  H03K19/17792

摘要： Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

摘要翻译： 提供了用于在可编程逻辑器件上选择性地互连逻辑的可编程互连组布置。 互连组可以被编程为在设备上的各种导体之间路由信号，并且将信号从设备上的各种逻辑区域路由到各种导体。 互连组提供路由灵活性和效率，而不需要使用过多的互连资源。

公开(公告)号：US06323677B1

公开(公告)日：2001-11-27

申请号：US09542211

申请日：2000-04-04

申请人： Christopher F. Lane ,  Srinivas T. Reddy ,  Richard G. Cliff ,  Ketan H. Zaveri ,  Bruce B. Pedersen ,  Kerry Veenstra

发明人： Christopher F. Lane ,  Srinivas T. Reddy ,  Richard G. Cliff ,  Ketan H. Zaveri ,  Bruce B. Pedersen ,  Kerry Veenstra

IPC分类号： H03K19173

CPC分类号： H03K19/17792 ,  H03K19/17728 ,  H03K19/17732

摘要： In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

摘要翻译： 为了便于可编程逻辑器件中的乘法性能，这些器件的各个逻辑模块被构造成使得一个逻辑模块可以执行（至少）二进制乘法的一个位置和完全二进制加法的一个位置。 这使得可以减少执行乘法所需的逻辑模块的数量。 它还减少了乘法中使用的模块间连接的数量，从而倾向于减少执行乘法所需的时间。

公开(公告)号：US06798242B2

公开(公告)日：2004-09-28

申请号：US10426991

申请日：2003-04-29

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US06577160B2

公开(公告)日：2003-06-10

申请号：US10170026

申请日：2002-06-10

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联。 本地导体与每个区域相关联。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US06300794B1

公开(公告)日：2001-10-09

申请号：US09488025

申请日：2000-01-20

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US6107824A

公开(公告)日：2000-08-22

申请号：US86302

申请日：1998-05-28

申请人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

发明人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

IPC分类号： H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/17792

摘要： Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.