公开(公告)号：US06480438B1

公开(公告)日：2002-11-12

申请号：US09881439

申请日：2001-06-12

申请人： Eungjoon Park

发明人： Eungjoon Park

IPC分类号： G11C800

CPC分类号： G11C16/24 ,  G11C13/0004 ,  G11C16/08 ,  G11C2213/72

摘要： To provide equal cell programming conditions, the integrated circuit device has a number of bitline compensation elements each coupled in series with a separate bitline, and a number of wordline compensation elements each coupled in series with a separate wordline. The resistances in these compensation elements are such that a variation in a sum of (1) the resistance along the corresponding bitline of a cell between the first terminal of the cell and a far terminal of the bitline compensation element that is coupled to the corresponding bitline and (2) the resistance along the corresponding wordline of the cell between a second terminal of the cell and a far terminal of the wordline compensation element that is coupled to the corresponding wordline, is minimized across the cells of the array.

摘要翻译： 为了提供相等的单元编程条件，集成电路器件具有多个位线补偿元件，每个位线补偿元件与单独的位线串联耦合，并且多个字线补偿元件分别与单独的字线串联耦合。 这些补偿元件中的电阻使得（1）沿着单元的第一端子与位线补偿元件的远端之间的单元的对应位线的电阻的和的变化，该位线耦合到相应的位线 和（2）沿单元的第二端子和耦合到对应的字线的字线补偿元件的远端之间的单元的对应字线的电阻在阵列的单元中被最小化。

公开(公告)号：US20120084491A1

公开(公告)日：2012-04-05

申请号：US13250077

申请日：2011-09-30

申请人： Eungjoon Park ,  Robin John Jigour ,  Jooweon Park ,  Masaru Yano

发明人： Eungjoon Park ,  Robin John Jigour ,  Jooweon Park ,  Masaru Yano

IPC分类号： G06F12/02

CPC分类号： G06F3/061 ,  G06F3/0608 ,  G06F3/0658 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C11/005 ,  G11C16/0416 ,  G11C16/0483 ,  G11C2216/30

摘要： A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

摘要翻译： 用于代码和数据存储的快闪存储器包括具有快速读取访问和用于执行的适用性的代码存储器阵列，具有低位成本和高密度存储的特性的数据存储器阵列，以及提供对两者的访问的适当接口 代码和数据。 代码存储器阵列可以是NOR阵列或性能增强的NAND阵列。 存储器可以在单个芯片封装或多芯片封装解决方案中实现。

公开(公告)号：US07449350B2

公开(公告)日：2008-11-11

申请号：US11614252

申请日：2006-12-21

申请人： Ali Pourkeramati ,  Eungjoon Park

发明人： Ali Pourkeramati ,  Eungjoon Park

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L2224/05554

摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

摘要翻译： 根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。 多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘和用于接收测试控制信号的第三接触焊盘。 第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。 探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。 在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

公开(公告)号：US20070102701A1

公开(公告)日：2007-05-10

申请号：US11614241

申请日：2006-12-21

申请人： Ali Pourkeramati ,  Eungjoon Park

发明人： Ali Pourkeramati ,  Eungjoon Park

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L2224/05554

摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

摘要翻译： 根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。 多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘以及用于接收测试控制信号的第三接触焊盘。 第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。 探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。 在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

公开(公告)号：US20070099312A1

公开(公告)日：2007-05-03

申请号：US11614252

申请日：2006-12-21

申请人： Ali Pourkeramati ,  Eungjoon Park

发明人： Ali Pourkeramati ,  Eungjoon Park

IPC分类号： H01L21/00

CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L2224/05554

摘要： In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

摘要翻译： 根据本发明的实施例，半导体晶片具有多个具有电路和多个接触焊盘的管芯。 多个接触焊盘包括用于接收电源电压的第一接触焊盘，用于接收接地电压的第二接触焊盘和用于接收测试控制信号的第三接触焊盘。 第三接触垫连接到嵌入在相应管芯上的可编程自检引擎（PSTE），使得测试控制信号激活PSTE以启动自检。 探针卡具有多组探针，每组探针具有三个探针，用于接触相应数量的多个管芯之一的第一，第二和第三接触焊盘。 在晶片测试期间，多组探针与相应数量的模具接触，使得在相应数量的模具中同时进行自检。

公开(公告)号：US06584016B2

公开(公告)日：2003-06-24

申请号：US09938266

申请日：2001-08-23

申请人： Eungjoon Park

发明人： Eungjoon Park

IPC分类号： G11C1134

CPC分类号： G11C16/0416

摘要： In accordance with an embodiment of the present invention, an array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a stack of floating gate and select gate extending over the channel region, the select gate of the cells along each row being connected together to form a wordline. Each of a plurality of data lines is coupled to the drain region of at least a portion of a column of cells. Each of a plurality of source lines is coupled to a source region of a plurality of cells along at least a portion of a row of cells, wherein injection of hot electrons from a portion of the channel region near the source region to the floating gate is induced in a selected memory cell in the array by applying a first voltage to a selected data line to which the drain of the selected memory cell is coupled, a second positive voltage to a word line to which the selected gate of the selected memory cell is coupled, and a third positive voltage to a source line to which the source of the selected memory cell is coupled, wherein the injection of hot electrons increases a threshold voltage of the selected cell.

公开(公告)号：US06501684B1

公开(公告)日：2002-12-31

申请号：US09668431

申请日：2000-09-22

申请人： Eungjoon Park ,  Ali Pourkeramati

发明人： Eungjoon Park ,  Ali Pourkeramati

IPC分类号： G11C1604

CPC分类号： G11C16/0433 ,  G11C16/0408

摘要： In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.

公开(公告)号：US5886566A

公开(公告)日：1999-03-23

申请号：US917008

申请日：1997-08-21

申请人： Eungjoon Park ,  Hsi-Hsien Hung

发明人： Eungjoon Park ,  Hsi-Hsien Hung

IPC分类号： G05F3/24 ,  G11C5/14 ,  H02M3/07 ,  G05F3/02

CPC分类号： G11C5/145 ,  H02M3/073 ,  G05F3/247

摘要： An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock terminal to the gate of the pass transistor, and a diode from the transfer stage output to ground. When the transfer stage input goes low, charge is coupled through the resistor to pre-charge the gate of the pass transistor. The resistor has a higher junction breakdown voltage than a transistor which allows the gate of the pass transistor to be driven to a larger voltage. To provide sufficient charge to turn on the pass transistor, a logic high level greater than the power supply, such as 2 VCC, can be used for the clock signal coupled through the capacitor configured transistor to the gate of the pass transistor. To prevent the 2 VCC logic high level from forward biasing the p-n junction formed by the source and drain of the PMOS capacitor configured transistor with the well, the source, drain and well are coupled together. The charge transfer stage also includes a p-n junction diode coupled from the output of the stage to ground.

摘要翻译： 描述了具有扩展的输出电压范围和高电荷转移效率的改进的电荷转移级。 电荷转移阶段可以实现为四相时钟负电荷泵系统中的输出级。 电荷传输级包括耦合传输级输入和输出的PMOS传输晶体管，传输级输入和传输晶体管栅极之间的电阻器，时钟端子，将时钟端子耦合到传输晶体管的栅极的电容器配置的PMOS晶体管 ，以及从转移级输出到地的二极管。 当传输级输入变为低电平时，电荷通过电阻耦合来对传输晶体管的栅极进行预充电。 电阻器具有比允许传输晶体管的栅极被驱动到更大电压的晶体管更高的结击穿电压。 为了提供足够的电荷来接通传输晶体管，可以将大于电源的逻辑高电平（例如2 VCC）用于通过电容器配置的晶体管耦合到传输晶体管的栅极的时钟信号。 为了防止2 VCC逻辑高电平正向偏置由PMOS电容器配置晶体管的源极和漏极与阱形成的p-n结，源极，漏极和阱耦合在一起。 电荷转移级还包括从级的输出端耦合到地的p-n结二极管。

公开(公告)号：US09021182B2

公开(公告)日：2015-04-28

申请号：US13250077

申请日：2011-09-30

申请人： Eungjoon Park ,  Robin John Jigour ,  Jooweon Park ,  Masaru Yano

发明人： Eungjoon Park ,  Robin John Jigour ,  Jooweon Park ,  Masaru Yano

IPC分类号： G06F12/02 ,  G11C11/00 ,  G11C16/04

CPC分类号： G06F3/061 ,  G06F3/0608 ,  G06F3/0658 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C11/005 ,  G11C16/0416 ,  G11C16/0483 ,  G11C2216/30

摘要： A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

摘要翻译： 用于代码和数据存储的快闪存储器包括具有快速读取访问和用于执行的适用性的代码存储器阵列，具有低位成本和高密度存储的特性的数据存储器阵列，以及提供对两者的访问的适当接口 代码和数据。 代码存储器阵列可以是NOR阵列或性能增强的NAND阵列。 存储器可以在单个芯片封装或多芯片封装解决方案中实现。

公开(公告)号：US20100049948A1

公开(公告)日：2010-02-25

申请号：US12459590

申请日：2009-07-02

申请人： Robin J. Jigour ,  Eungjoon Park ,  Joo Weon Park ,  Jong Seuk Lee

发明人： Robin J. Jigour ,  Eungjoon Park ,  Joo Weon Park ,  Jong Seuk Lee

IPC分类号： G06F9/30 ,  G06F12/00 ,  G06F12/02

CPC分类号： G11C7/1045 ,  G11C8/04 ,  G11C16/26 ,  G11C2207/108 ,  G11C2216/30

摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

摘要翻译： 串行闪存具有多个可配置引脚，其中至少一个可选择性地配置用于单位串行数据传输或多位串行数据传输。 在单位串行模式下，数据传输通过引脚逐位传输。 在多位串行模式下，通过各个引脚一次传输多个连续位。 串行闪存可能具有16个或更少的引脚，甚至8个或更少的引脚，因此可以使用低引脚数封装，例如8引脚或16引脚SOIC封装和8接点MLP / QFN / SON封装 。 单位串行类型协议的可用性支持与许多现有系统的兼容性，而多位串行类型协议的可用性使得串行闪存能够在可以支持它们的系统中提供数据传输速率 显着快于标准串行闪存的可用性。