公开(公告)号：US08410820B2

公开(公告)日：2013-04-02

申请号：US13026904

申请日：2011-02-14

Applicant: Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: G01R19/00 ,  G11C7/00 ,  H03K3/45

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

公开(公告)号：US08401502B2

公开(公告)日：2013-03-19

申请号：US12536024

申请日：2009-08-05

Applicant: Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

Inventor： Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

IPC: H04B1/04

CPC classification number: H04B1/581

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The transmitter includes a plurality of current cells. Each cell is configurable for operating in different modes. The method includes determining a first probability associated with transmitting data at a particular symbolic level and determining a second probability associated with each cell being used during a transmission at the particular symbolic level. Next, one of the modes for each cell is selected in accordance with anticipated performance requirements. An average current of the transmitter is then calculated based upon the determined first and second probabilities and the selected modes.

公开(公告)号：US20090121910A1

公开(公告)日：2009-05-14

申请号：US12204482

申请日：2008-09-04

Applicant: Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

Inventor： Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

IPC: H03M1/66

CPC classification number: H03F3/45183 ,  H03F2203/45466

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

Abstract translation: 提供了一种用于控制具有发射机的收发机中的电流特性的方法和系统。 该方法包括在时间上识别来自特定当前小区之前的相邻当前小区的相位控制信号，并且将来自前一小区的相位控制信号与来自特定当前小区的相位控制信号进行逻辑或运算。

公开(公告)号：US07352215B2

公开(公告)日：2008-04-01

申请号：US10649808

申请日：2003-08-28

Applicant: Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: G01R19/00 ,  G11C7/00 ,  H03K3/45

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract translation: 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

公开(公告)号：US07324038B2

公开(公告)日：2008-01-29

申请号：US10625702

申请日：2003-07-24

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Ruby van de Plassche ,  Marcel Lugthart

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Ruby van de Plassche ,  Marcel Lugthart

IPC: H03M1/12

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

公开(公告)号：US07135942B2

公开(公告)日：2006-11-14

申请号：US10694952

申请日：2003-10-29

Applicant: Jan R Westra ,  Jan Mulder

Inventor： Jan R Westra ,  Jan Mulder

IPC: H03H7/24 ,  H03G3/10

CPC classification number: H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

公开(公告)号：US20050093643A1

公开(公告)日：2005-05-05

申请号：US10694952

申请日：2003-10-29

Applicant: Jan Westra ,  Jan Mulder

Inventor： Jan Westra ,  Jan Mulder

IPC: H01P1/22 ,  H03H7/24

CPC classification number: H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

Abstract translation: 可编程增益衰减器包括终端电阻。 第一终端开关将终端电阻器的一侧连接到第一输出。 第二终端开关将终端电阻器的另一侧连接到第二输出端。 在第一输入和终端电阻的第一侧之间布置第一电阻梯。 第一多个开关将来自第一电阻梯的相应抽头连接到第一输出。 在第二输入端和终端电阻器的第二侧之间布置第二电阻梯。 第二多个开关将来自第二电阻梯的相应抽头连接到第二输出。 第一多个开关的第一开关被接通，接着是第一多个开关的第二开关被关闭，随后开启第一组开关的第三开关。 第二多个开关的第一开关被接通，随后是第二多个开关的第二开关被关闭，随后是第二多个开关的第三开关导通。

公开(公告)号：US06888483B2

公开(公告)日：2005-05-03

申请号：US10893999

申请日：2004-07-20

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: H03K17/041 ,  H03M1/06 ,  H03M1/08 ,  H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/00

CPC classification number: H03M1/0863 ,  H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/36 ,  H03M1/365

Abstract: An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.

Abstract translation: 输入级包括在每个阵列中串联布置的多个自动调零放大器阵列，其中每个自动调零放大器接收前一自动调零放大器的输出，其中每个阵列放大器中的第一自动调零放大器接收输入信号和对应的参考电压 其输入，并且其中至少一个自动调零放大器包括接收对应于输出信号的信号的电路，所述电路在时钟相位phi 2 <！ - SIPO - >并且在时钟相位phi1 <1>中基本上拒绝对应于输出信号的信号。

公开(公告)号：US06876318B2

公开(公告)日：2005-04-05

申请号：US10798552

申请日：2004-03-12

Applicant: Jan Mulder ,  Franciscus M. L. van der Goes

Inventor： Jan Mulder ,  Franciscus M. L. van der Goes

IPC: H03M1/08 ,  H03M1/36 ,  H03M1/06

CPC classification number: H03M1/0863 ,  H03M1/36

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract translation: 一种用于减少具有比较器阵列的模数转换器中的位错误的方法。 第一和第二比较器的输出在异或门的输入中被接收。 第一和第二比较器由阵列中的第三比较器分开。 异或门的输出用于确定第三比较器是否处于亚稳态。 如果第三比较器处于亚稳态，则第三比较器的锁存电路的偏置电流增加，以增加第三比较器转变到稳定状态的速率。

公开(公告)号：US06873210B2

公开(公告)日：2005-03-29

申请号：US10791878

申请日：2004-03-04

Applicant: Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

Inventor： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

IPC: H03H11/32 ,  H03F3/45

CPC classification number: H03H11/32

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

Abstract translation: 提供了在提供共模电压控制的同时执行单端到差分转换的电路。 电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。 稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。 比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。 调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。