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    Storage Elements with Disguised Configurations and Methods of Using the Same
    12.
    发明申请
    Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
    具有伪装配置的存储元件及其使用方法

    公开(公告)号：US20080067600A1

    公开(公告)日：2008-03-20

    申请号：US11533191

    申请日：2006-09-19

    申请人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01L23/62

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。 提供了许多其他方面。

    SOI hybrid structure with selective epitaxial growth of silicon
    14.
    发明授权
    SOI hybrid structure with selective epitaxial growth of silicon 有权

    公开(公告)号：US06555891B1

    公开(公告)日：2003-04-29

    申请号：US09690674

    申请日：2000-10-17

    申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    IPC分类号： H01L2900

    CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

    摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

    Trench field shield in trench isolation
    16.
    发明授权
    Trench field shield in trench isolation 失效
    沟槽隔离屏蔽沟槽

    公开(公告)号：US06420749B1

    公开(公告)日：2002-07-16

    申请号：US09602427

    申请日：2000-06-23

    申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    IPC分类号： H01L27108

    CPC分类号： H01L21/823481 ,  H01L21/743 ,  H01L21/76232 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/10897

    摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.

    摘要翻译： 一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间​​的沟槽的绝缘体。 第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。 第一装置可以独立于第二装置而被偏置。 接触件在衬底的表面上方延伸。 第一接触件邻接第一器件和第一导电侧壁间隔物。 绝缘体将导电侧墙隔离开。 第一接触件可以在第一导体和第二导体之间等距。 导电侧壁间隔件包括场屏蔽。

    Method of forming bitline diffusion halo under gate conductor ledge
    18.
    发明授权
    Method of forming bitline diffusion halo under gate conductor ledge 失效
    在栅极导体突起处形成位线扩散晕的方法

    公开(公告)号：US06274441B1

    公开(公告)日：2001-08-14

    申请号：US09560073

    申请日：2000-04-27

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  William R. Tonti

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  William R. Tonti

    IPC分类号： H01L2170

    CPC分类号： H01L29/1045 ,  H01L21/266 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

    摘要： A method for fabricating a MOSFET device including a halo implant comprising providing a semiconductor substrate, a gate insulator layer, a conductor layer, an overlying silicide layer, and an insulating cap; patterning and etching the silicide layer and the insulating cap; providing insulating spacers along sides of said silicide layer and insulating cap; implanting node and bitline N+ diffusion regions; patterning a photoresist layer to protect the node diffusion region and supporting PFET source and drain regions and expose the bitline diffusion region and NFET source and drain regions; etching exposed spacer material from the side of said silicide layer and insulating cap; implanting a P-type impurity halo implant into the exposed bitline diffusion region and supporting NFET source and drain regions; and stripping the photoresist layer and providing an insulating spacer along the exposed side of said silicide layer and insulating cap.

    摘要翻译： 一种制造包括卤素注入的MOSFET器件的方法，包括提供半导体衬底，栅极绝缘体层，导体层，上覆硅化物层和绝缘帽; 图案化和蚀刻硅化物层和绝缘帽; 在所述硅化物层和绝缘盖的侧面提供绝缘垫片; 植入节点和位线N +扩散区域; 图案化光致抗蚀剂层以保护节点扩散区域并支持PFET源极和漏极区域并暴露位线扩散区域和NFET源极和漏极区域; 从所述硅化物层和绝缘盖的侧面蚀刻暴露的间隔物材料; 将P型杂质卤素注入植入暴露的位线扩散区并支持NFET源极和漏极区; 并剥离光致抗蚀剂层，并沿着所述硅化物层和绝缘帽的暴露侧提供绝缘间隔物。

    Redundant input/output driver circuit
    19.
    发明授权
    Redundant input/output driver circuit 失效
    冗余输入/输出驱动电路

    公开(公告)号：US06177809B1

    公开(公告)日：2001-01-23

    申请号：US09322470

    申请日：1999-05-28

    申请人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    发明人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    IPC分类号： H03K19094

    CPC分类号： H03K19/00384 ,  H03K19/0005

    摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.

    摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。