公开(公告)号：US20130147007A1

公开(公告)日：2013-06-13

申请号：US13316104

申请日：2011-12-09

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/06 ,  H01L21/02

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

摘要翻译： 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

公开(公告)号：US08232162B2

公开(公告)日：2012-07-31

申请号：US12880419

申请日：2010-09-13

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang ,  Yanli Zhang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L21/8242

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.

摘要翻译： 形成半导体器件的深沟槽结构的方法包括在半导体衬底上形成掩模层。 通过对掩模层进行构图来形成掩模层中的开口，并且使用掩模层中的图案化开口在半导体衬底中形成深沟槽。 牺牲填充材料形成在掩模层上并进入深沟槽中。 牺牲填充材料的第一部分从深沟槽凹陷，并且第一掺杂剂注入在半导体衬底中形成第一掺杂区域。 牺牲填充材料的第二部分从深沟槽凹陷，并且第二掺杂剂注入在半导体衬底中形成第二掺杂区，其中第二掺杂区形成在第一掺杂区的下方，使得第二掺杂区和第一掺杂区 掺杂区域彼此邻接。

公开(公告)号：US08809994B2

公开(公告)日：2014-08-19

申请号：US13316104

申请日：2011-12-09

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/70

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

摘要翻译： 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

公开(公告)号：US20120306049A1

公开(公告)日：2012-12-06

申请号：US13153538

申请日：2011-06-06

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/20 ,  H01L27/06

CPC分类号： H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

摘要翻译： 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

公开(公告)号：US20120305998A1

公开(公告)日：2012-12-06

申请号：US13118881

申请日：2011-05-31

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L29/92 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1203

摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

摘要翻译： 在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料 的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。 可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

公开(公告)号：US20110215412A1

公开(公告)日：2011-09-08

申请号：US12717375

申请日：2010-03-04

申请人： Chengwen Pei ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/22

CPC分类号： H01L21/22 ,  H01L21/8238 ,  H01L27/092

摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

摘要翻译： 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

公开(公告)号：US08575670B2

公开(公告)日：2013-11-05

申请号：US13316056

申请日：2011-12-09

申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L27/10861 ,  H01L28/91 ,  H01L29/945

摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.

摘要翻译： 一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。 电容器存在于沟槽的下部。 电介质垫片存在于沟槽上部的侧壁上。 介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。 导电材料填充物存在于沟槽的上部。 半导体器件存在于与沟槽相邻的SOI层上。 半导体器件通过导电材料填充与电容器电连通。

公开(公告)号：US09048339B2

公开(公告)日：2015-06-02

申请号：US13606448

申请日：2012-09-07

申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/84 ,  H01L29/66 ,  H01L27/108 ,  H01L27/12

CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.

摘要翻译： 提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。 该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂 散装衬底形成掩埋板。 该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部， 去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

公开(公告)号：US20140061793A1

公开(公告)日：2014-03-06

申请号：US13597752

申请日：2012-08-29

申请人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/336

CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

摘要翻译： 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

公开(公告)号：US08637365B2

公开(公告)日：2014-01-28

申请号：US13489572

申请日：2012-06-06

申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： H01L29/0649 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.