公开(公告)号：US08563370B2

公开(公告)日：2013-10-22

申请号：US13384215

申请日：2011-07-04

申请人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

发明人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

IPC分类号： H01L21/338

CPC分类号： H01L29/78696 ,  H01L21/76289 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772

摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.

摘要翻译： 提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。 该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

公开(公告)号：US20130017654A1

公开(公告)日：2013-01-17

申请号：US13266791

申请日：2011-07-15

申请人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

发明人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

IPC分类号： H01L21/336 ,  B82Y99/00

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L29/775

摘要： The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.

摘要翻译： 本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。 该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。 本发明与CMOS工艺流程兼容。 空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

公开(公告)号：US20120115297A1

公开(公告)日：2012-05-10

申请号：US13133643

申请日：2010-09-25

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差引起的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点

公开(公告)号：US08288238B2

公开(公告)日：2012-10-16

申请号：US13133643

申请日：2010-09-25

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点

公开(公告)号：US20120238097A1

公开(公告)日：2012-09-20

申请号：US13513852

申请日：2011-09-29

申请人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

发明人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  B82Y30/00 ,  B82Y40/00 ,  H01L28/20

摘要： Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.

摘要翻译： 这里公开了一种属于超大规模集成电路制造技术领域的细线的制造方法。 在本发明中，执行三个修整掩模处理以有效地改善线的轮廓并大大降低线的LER（线边缘粗糙度）。 同时，本发明与侧壁工艺相结合，可以成功制作纳米级细线，精确控制为20nm。 因此，可以在衬底上制造具有优化的LER的纳米级线。

公开(公告)号：US20130001655A1

公开(公告)日：2013-01-03

申请号：US13582624

申请日：2011-08-17

申请人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

发明人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

IPC分类号： H01L23/38 ,  H01L29/80

CPC分类号： H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.

摘要翻译： 本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。 散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。 在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线 漏极端子相对于漏极端子施加低电位。 在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是 相对于源极端子施加较低的电位。 通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此 在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

公开(公告)号：US08598636B2

公开(公告)日：2013-12-03

申请号：US13582624

申请日：2011-08-17

申请人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

发明人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

IPC分类号： H01L29/80

CPC分类号： H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.

摘要翻译： 本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。 散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。 在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线 漏极端子相对于漏极端子施加低电位。 在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是 相对于源极端子施加较低的电位。 通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此 在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

公开(公告)号：US20130043515A1

公开(公告)日：2013-02-21

申请号：US13255443

申请日：2011-03-23

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Ai ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Ai ,  Xing Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.

摘要翻译： 本发明公开了一种应变通道场效应晶体管及其制造方法。 场效应晶体管包括衬底，源极/漏极，栅极介电层和栅极，其特征在于，L形复合隔离层，其包围与沟道相邻的源极/漏极的侧面的一部分 并且源/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的L形绝缘薄层和与源极和漏极直接接触的L形高应力层。 这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力 。