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    Electronic apparatus and controlling method thereof
    12.
    发明授权
    Electronic apparatus and controlling method thereof 有权

    公开(公告)号：US11481586B2

    公开(公告)日：2022-10-25

    申请号：US17494070

    申请日：2021-10-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongmin Tai ,  Insang Cho ,  Chanyoung Hwang

    IPC: G06K9/62 ,  G06N3/04 ,  G06N3/08 ,  G06T3/40 ,  G06T7/00

    Abstract: An electronic apparatus may include a memory that stores first information regarding a plurality of first artificial intelligence models trained to perform image processing differently from each other and second information regarding a second artificial intelligence model trained to identify a type of an image by predicting a processing result of the image by each of the plurality of first artificial intelligence models. The electronic apparatus may further include a processor configured to identify a type of an input image by inputting the input image to the second artificial intelligence model stored in the memory, and process the input image by inputting the input image to one of the plurality of first intelligence models stored in the memory based on the identified type.

    ELECTRONIC DEVICE AND METHOD FOR CONTROLLING SHAREABLE CACHE MEMORY THEREOF
    14.
    发明申请
    ELECTRONIC DEVICE AND METHOD FOR CONTROLLING SHAREABLE CACHE MEMORY THEREOF 审中-公开
    用于控制其可访问的高速缓存存储器的电子设备和方法

    公开(公告)号：US20160154735A1

    公开(公告)日：2016-06-02

    申请号：US14957520

    申请日：2015-12-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanyoung Hwang ,  Seungjin Yang

    IPC: G06F12/08

    CPC classification number: G06F12/084 ,  G06F1/32 ,  G06F1/3275 ,  G06F12/0842 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/20 ,  G06F2212/455 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.

    Abstract translation: 提供了一种用于控制电子设备的共享高速缓冲存储器的电子设备和方法。 电子设备包括中央处理单元，该中央处理单元包括至少一个核心处理器，至少一个模块和包括控制器的可共享高速缓存存储器，其中如果中央处理器将控制器作为中央处理单元的高速缓存存储器， 单元处于工作模式，并且其中如果中央处理单元的至少一个核心处理器转换到休眠模式，则控制器使得可共享高速缓冲存储器作为至少一个模块的缓冲器。

    ELECTRONIC DEVICE, ON-CHIP MEMORY AND METHOD OF OPERATING THE ON-CHIP MEMORY
    15.
    发明申请
    ELECTRONIC DEVICE, ON-CHIP MEMORY AND METHOD OF OPERATING THE ON-CHIP MEMORY 审中-公开
    电子设备，片上存储器和操作片上存储器的方法

    公开(公告)号：US20160041791A1

    公开(公告)日：2016-02-11

    申请号：US14821663

    申请日：2015-08-07

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Chanyoung Hwang ,  Seungjin Yang

    IPC: G06F3/06

    CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0673 ,  G06F21/79

    Abstract: An electronic device, an on-chip memory and a method of operating the on-chip memory are disclosed. The on-chip memory including an on-chip memory comprises: a plurality of design Intellectual Property (IPs), a memory that includes a storage area and a processor connected to the memory, wherein the processor is configured to monitor a memory traffic of at least one IP among the plurality of design IPs, and control usage of a storage area based on a result of the monitoring. According to the electronic device, the on-chip memory and the method of operating the on-chip memory of the present disclosure, in an AP-CP one chip structure, a stable communication is secured, memory latency is secured for a code required to process a real time of a CP, and in the AP-CP one chip structure, a communication bandwidth is improved.

    Abstract translation: 公开了电子设备，片上存储器和操作片上存储器的方法。 包括片上存储器的片上存储器包括：多个设计知识产权（IP），包括存储区域的存储器和连接到存储器的处理器，其中处理器被配置为监视存储器的存储器业务量 所述多个设计IP中的至少一个IP，以及基于所述监视的结果来控制对存储区域的使用。 根据电子设备，片上存储器和本公开的片上存储器的操作方法，在AP-CP单芯片结构中，确保稳定的通信，保证存储器等待时间为 处理CP的实时，并且在AP-CP单芯片结构中，提高了通信带宽。

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