Circuit for adjusting resonance frequency and electronic device including same

    公开(公告)号:US11824529B2

    公开(公告)日:2023-11-21

    申请号:US16960148

    申请日:2019-01-03

    Abstract: An electronic device according to an embodiment includes a first touch key disposed in a first area of the electronic device, a second touch key disposed in a second area of the electronic device, an antenna, a communication circuit, electrically connected to the antenna, for transmitting or receiving a signal using the antenna, a sensing circuit for sensing an external object corresponding to the electronic device, a frequency adjustment circuit, electrically connected to the antenna, adjusting a resonance frequency of the antenna, and a processor wherein the processor detects the external object using the sensing circuit while communicating with an external device using the communication circuit, in response to detecting the external object, detects an amount of change of capacitance corresponding to the external object using the first touch key or the second touch key. If a first amount of change of capacitance detected through the first touch key is greater than a second amount of change of capacitance detected through the second touch key, the electronic device communicates using the communication circuit wherein the frequency adjustment circuit is designated in a first mode. If the second amount of change of capacitance detected through the second touch key is greater than the second amount of change of capacitance detected through the first touch key, the electronic device communicates using the communication circuit wherein the frequency adjustment circuit is designated in a second mode. In addition, various other embodiments are possible.

    MEMORY SYSTEM, METHOD OF OPERATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20240385925A1

    公开(公告)日:2024-11-21

    申请号:US18543737

    申请日:2023-12-18

    Abstract: A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller includes a plurality of volatile memory devices; and a memory controller configured to control the plurality of volatile memory devices, wherein the memory controller includes: a host interface configured to communicate with a host device based on a Compute eXpress Link (CXL) communication protocol; an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level being error correction levels based on cell reliability information and data reliability request information which are associated with the cache line data; and an ECC engine configured to, based on the ECC control signal indicating the first correction level, generate first parity symbols associated with the cache line data, and based on the ECC control signal indicating the second correction level, generate additional parity symbols.

    Voltage trimming circuit
    17.
    发明授权

    公开(公告)号:US12062404B2

    公开(公告)日:2024-08-13

    申请号:US18239548

    申请日:2023-08-29

    CPC classification number: G11C17/18 G11C17/16 G11C29/08

    Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

    Wireless power receiving device, wireless power transmitting device, and control method therefor

    公开(公告)号:US11894692B2

    公开(公告)日:2024-02-06

    申请号:US17267996

    申请日:2019-08-14

    CPC classification number: H02J50/20 H02J50/40 H02J50/80 H02J50/90

    Abstract: A wireless power receiving device, according to the disclosure, comprises: at least one power receiving antenna for sequentially receiving a plurality of different RF waves formed by a wireless power transmitting device; a communication circuit; and at least one processor, wherein the at least one processor is configured to confirm a plurality of pieces of strength information that indicates the strength of each of the plurality of different RF waves, confirm a plurality of pieces of phase information corresponding to each of the plurality of different RF waves, confirm, on the basis of the plurality of pieces of strength information and the plurality of pieces of phase information, an optimum phase value such that a received RF wave has a maximum strength, and transmit a communication signal including information about the optimum phase value to the wireless power transmitting device through the communication circuit. Additional various embodiments are possible.

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