公开(公告)号：US20230095469A1

公开(公告)日：2023-03-30

申请号：US17849783

申请日：2022-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohee Hwang ,  Taehun Kim ,  Minkyung Bae ,  Nayeong Yun

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A vertical non-volatile memory device includes: a memory stack structure including gate lines and interlayer insulating layers and a channel hole extending in a stacking direction; a channel layer in the channel hole and extending in the stacking direction; and an information storage structure including a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction from the gate lines to the channel layer, wherein the composite blocking insulating layer includes a metal oxide having a higher dielectric constant than silicon oxide, and the composite blocking insulating layer includes a first blocking insulating layer on sides of the gate lines and a second blocking insulating layer that is between the first blocking insulating layer and the charge storage layer and has a lower oxidation density than the first blocking insulating layer.

公开(公告)号：US11114165B2

公开(公告)日：2021-09-07

申请号：US16821225

申请日：2020-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohee Hwang ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Bongyong Lee

IPC: G11C16/32 ,  G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/12 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

公开(公告)号：US10923195B2

公开(公告)日：2021-02-16

申请号：US16686327

申请日：2019-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyung Bae ,  Tae Hun Kim ,  Myunghun Woo ,  Bongyong Lee ,  Doohee Hwang

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11582

Abstract: An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.