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    Semiconductor memory devices and memory systems including the same
    1.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US11495280B2

    公开(公告)日：2022-11-08

    申请号：US17399349

    申请日：2021-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeongseok Seo ,  Kwanghyun Kim ,  Chikook Kim ,  Seungwoo Ryu ,  Doohee Hwang

    IPC: G11C11/40 ,  G11C11/4072 ,  H01L25/065

    Abstract: A semiconductor memory device includes an external resistor provided on a board and a plurality of memory dies mounted on the board, designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation during an initialization sequence of the semiconductor memory device and stores, in a first register set therein, first calibration data, a first voltage and a first temperature. Each of the slave dies, after the first impedance calibration operation is completed, performs a second impedance calibration operation during the initialization sequence and stores, in a second register set therein, second calibration data associated with the second impedance calibration operation and offset data corresponding to a difference between the first calibration data and the second calibration data.

    Memory system performing hammer refresh operation and method of controlling refresh of memory device
    3.
    发明授权
    Memory system performing hammer refresh operation and method of controlling refresh of memory device 有权

    公开(公告)号：US11508429B2

    公开(公告)日：2022-11-22

    申请号：US17399402

    申请日：2021-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonkyu Choi ,  Dokyun Kim ,  Seongjin Lee ,  Doohee Hwang

    IPC: G11C11/406 ,  G11C7/10

    Abstract: A memory system includes a memory controller and a memory device. The memory controller generates refresh commands periodically by an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during a refresh cycle time. The memory device includes a memory cell array including memory cells connected to a plurality of wordlines, a temperature sensor configured to provide temperature information by measuring an operation temperature of the memory cell array and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller varies a hammer ratio of a unit hammer execution number of the hammer refresh operation executed during the refresh cycle time with respect to a unit normal execution number of the normal refresh operation executed during the refresh cycle time.

    Memory device and method of refreshing memory device based on temperature
    6.
    发明授权
    Memory device and method of refreshing memory device based on temperature 有权

    公开(公告)号：US11804254B2

    公开(公告)日：2023-10-31

    申请号：US17529900

    申请日：2021-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Saemi Song ,  Dokyun Kim ,  Yeonkyu Choi ,  Doohee Hwang

    IPC: G11C11/406

    CPC classification number: G11C11/40626 ,  G11C11/40615 ,  G11C11/40622

    Abstract: Provided are a memory device and a method of refreshing the memory device regardless of a refresh rate multiplier for a temperature. In response to a refresh command at each base refresh rate (tREFi) based on a measured temperature, a memory device refreshes M memory cell rows at room temperature, refreshes 2M memory cell rows at a high temperature, and refreshes (½)M memory cell rows at a low temperature. The memory device refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a refresh command applied after n skipped base refresh rates, and refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a pulling-in refresh command.

    VERTICAL NON-VOLATILE MEMORY DEVICES
    7.
    发明申请
    VERTICAL NON-VOLATILE MEMORY DEVICES 有权

    公开(公告)号：US20230095469A1

    公开(公告)日：2023-03-30

    申请号：US17849783

    申请日：2022-06-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Doohee Hwang ,  Taehun Kim ,  Minkyung Bae ,  Nayeong Yun

    IPC: H01L27/11582 ,  H01L27/11556

    Abstract: A vertical non-volatile memory device includes: a memory stack structure including gate lines and interlayer insulating layers and a channel hole extending in a stacking direction; a channel layer in the channel hole and extending in the stacking direction; and an information storage structure including a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction from the gate lines to the channel layer, wherein the composite blocking insulating layer includes a metal oxide having a higher dielectric constant than silicon oxide, and the composite blocking insulating layer includes a first blocking insulating layer on sides of the gate lines and a second blocking insulating layer that is between the first blocking insulating layer and the charge storage layer and has a lower oxidation density than the first blocking insulating layer.

    Nonvolatile memory device, an operating method thereof, and a storage system including the nonvolatile memory device
    9.
    发明授权
    Nonvolatile memory device, an operating method thereof, and a storage system including the nonvolatile memory device 有权

    公开(公告)号：US10923195B2

    公开(公告)日：2021-02-16

    申请号：US16686327

    申请日：2019-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minkyung Bae ,  Tae Hun Kim ,  Myunghun Woo ,  Bongyong Lee ,  Doohee Hwang

    IPC: G11C11/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11582

    Abstract: An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250040176A1

    公开(公告)日：2025-01-30

    申请号：US18629093

    申请日：2024-04-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngtaek Oh ,  Jiwoong Kim ,  Taehun Kim ,  Minkyung Bae ,  Seungjae Baik ,  Jaeduk Lee ,  Doohee Hwang

    IPC: H01L29/78 ,  H01L23/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/10 ,  H10B80/00

    Abstract: A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure. The cell structure includes a plurality of gate electrodes spaced apart from each other in a vertical direction, a channel structure passing through the plurality of gate electrodes and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end, and a common source layer covering the second end of the channel structure. The channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region that contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.

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