公开(公告)号：US20180006666A1

公开(公告)日：2018-01-04

申请号：US15638065

申请日：2017-06-29

Applicant: Samsung Electronics Co., Ltd. ,  Korea University Research and Business Foundation

Inventor： Chanhong Kim ,  Inkyu Lee ,  Hoon Lee ,  Ji Hwan Moon ,  Tae Seok Oh ,  Seok Ju Jang

IPC: H03M13/29 ,  H03M13/05 ,  H03M13/11 ,  H04L1/00

CPC classification number: H03M13/2906 ,  H03M13/05 ,  H03M13/1137 ,  H04L1/0058 ,  H04L1/0606 ,  H04L1/0643 ,  H04L1/0681

Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-generation (4G) communication system such as long term evolution (LTE). Disclosed are an apparatus and a method for a permutation of a block code in a wireless communication system. A method of operating a transmitting node in a wireless communication system includes: determining a permutation matrix according to a block code scheme; generating symbols corresponding to a plurality of antennas based on the block code scheme and the permutation matrix; and transmitting the symbols to a receiving node through the plurality of antennas. The permutation matrix is determined based on a number of blocks and an arrangement structure of the plurality of antennas, and the number of blocks comprises a number of sub-blocks within a code block corresponding to the permutation matrix.

公开(公告)号：US09118313B2

公开(公告)日：2015-08-25

申请号：US14466509

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Lee ,  Jin-Hee Park

IPC: G11C11/00 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/0005 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/12 ,  G11C2207/2254

Abstract: Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value of the calibration code, or is equal to or less than a lower critical value of the calibration code, and to generate an adjustment signal for adjusting a value of a termination resistance of a data output driver based on the determination result; and resistance calibration logic configured to provide the upper bit string to the self-adjustment logic, and to generate an updated calibration code by performing a calibration calculation based on the calibration code and a comparison signal generated according to a result of comparing a reference voltage and a voltage of a comparison target node.

Abstract translation: 提供了校准端接电阻的半导体存储器件，所述半导体存储器件包括自调整逻辑，其被配置为确定响应于校准开始信号产生的校准代码的高位位串的值是否等于或大于 校准代码的上临界值或者等于或小于校准代码的较低临界值，并且基于确定结果生成用于调整数据输出驱动器的终端电阻的值的调整信号; 以及电阻校准逻辑，被配置为将所述高位串提供给所述自调节逻辑，并且通过基于所述校准代码执行校准计算以及根据比较参考电压和 比较目标节点的电压。

公开(公告)号：US20130201778A1

公开(公告)日：2013-08-08

申请号：US13828604

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon Lee ,  Uk Song Kang ,  Hoe Ju Chung

IPC: G11C8/10 ,  G11C8/12

CPC classification number: G11C8/10 ,  G11C5/00 ,  G11C5/02 ,  G11C8/06 ,  G11C8/12

Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

Abstract translation: 半导体器件包括包括多个存储体的存储单元阵列和页面大小控制器。 页面尺寸控制器解码存储体选择地址或电源电压的一部分以及存储体选择地址的剩余部分，以使得多个存储体中的一个存储体使能或使多个存储体中的两个可以设置半导体的页面大小 设备。