公开(公告)号：US20230397432A1

公开(公告)日：2023-12-07

申请号：US18329197

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Hyunjae LEE ,  Dukhyun CHOE

IPC: H10B53/20 ,  H10B53/10 ,  G11C16/04 ,  H10B51/10 ,  H10B51/20

CPC classification number: H10B53/20 ,  H10B53/10 ,  G11C16/0483 ,  H10B51/10 ,  H10B51/20

Abstract: A memory device includes a plurality of gate electrodes spaced apart from each other in a first direction, a memory layer comprising a plurality of memory regions that protrude and extend in a second direction perpendicular to the first direction to face the plurality of gate electrodes, respectively, a plurality of first insulating layers extended to spaces between the plurality of memory regions between the plurality of gate electrodes, a channel layer disposed between the memory layer and the plurality of gate electrodes, the channel layer having a shape including a plurality of first regions surrounding the plurality of memory regions and a second region that connects the plurality of first regions to each other in the first direction, and a gate insulating layer arranged between the channel layer and the plurality of gate electrodes.

公开(公告)号：US20250056844A1

公开(公告)日：2025-02-13

申请号：US18761631

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Seunggeol NAM ,  Sijung YOO ,  Dukhyun CHOE

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H10B51/30

Abstract: Provided is a ferroelectric field effect transistor including a source region, a drain region, a channel provided between the source region and the drain region, a ferroelectric layer provided on the channel and including a ferroelectric material including an oxide of a first element, a gate-interposed layer provided on the ferroelectric layer and including a paraelectric material including an oxide of a second element different from the first element, and a gate electrode provided on the gate-interposed layer, wherein the gate-interposed layer includes a first interposed layer adjacent to the ferroelectric layer, and a second interposed layer adjacent to the gate electrode, the first interposed layer includes a mixture of the first element and the second element, and a ratio of the first element in the first interposed layer may be greater than a ratio of the first element in the ferroelectric layer.

公开(公告)号：US20240244848A1

公开(公告)日：2024-07-18

申请号：US18412793

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Jinseong HEO ,  Seunggeol NAM ,  Yunseong LEE ,  Dukhyun CHOE

IPC: H10B51/30 ,  H10B51/20

CPC classification number: H10B51/30 ,  H10B51/20

Abstract: Provided is a semiconductor device including a ferroelectric layer. The semiconductor device includes a channel layer including an n-type oxide semiconductor layer and a p-type oxide semiconductor layer, a ferroelectric layer disposed on the channel layer, a gate electrode disposed on the ferroelectric layer, and a reduced layer disposed on the channel layer and including an element having greater reducing power than a metal included in the channel layer.

公开(公告)号：US20240162346A1

公开(公告)日：2024-05-16

申请号：US18495220

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Jinseong HEO ,  Kihong KIM ,  Hyunjae LEE

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/78391 ,  H01L28/60 ,  H01L29/516 ,  H01L29/6684 ,  H10B12/31

Abstract: A field effect transistor includes a source region, a drain region, a channel between the source region and the drain region, a gate insulating layer configured to cover an upper surface of the channel, and a gate electrode configured to cover an upper surface of the gate insulating layer. The gate insulating layer includes a first region where a ferroelectric crystal structure is dominant and a second region where a non-ferroelectric structure is dominant. The gate electrode includes a first pattern region facing the first region of the gate insulating layer and a second pattern region facing the second region of the gate insulating layer.

公开(公告)号：US20240081080A1

公开(公告)日：2024-03-07

申请号：US18461266

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Jinseong HEO ,  Seunggeol NAM ,  Yunseong LEE ,  Dukhyun CHOE

IPC: H10B51/20

CPC classification number: H10B51/20

Abstract: A semiconductor device including a substrate, an interfacial layer on the substrate, a ferroelectric layer on the interfacial layer, a gate on the ferroelectric layer, and the nitride protective layer between the interfacial layer and the gate and being adjacent to the ferroelectric layer.

公开(公告)号：US20230186086A1

公开(公告)日：2023-06-15

申请号：US18063936

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Jinseong HEO ,  Seunggeol NAM ,  Hagyoul BAE ,  Hyunjae LEE

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: Provided is a neural network device including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells arranged at points where the plurality of word lines and the plurality of bit lines intersect one another. Each of the plurality of memory cells includes at least two ferroelectric memories connected in parallel along a word line corresponding to each of the plurality of memory cells.

公开(公告)号：US20230155026A1

公开(公告)日：2023-05-18

申请号：US17986237

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Dukhyun CHOE ,  Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H01L29/78 ,  H01L27/108 ,  H01L27/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/10805 ,  H01L27/2436 ,  H01L29/516 ,  H01L29/7833 ,  H01L29/6684

Abstract: Provided are a semiconductor device and a semiconductor apparatus including the semiconductor device. The semiconductor device includes a substrate having a channel layer comprising a dopant, a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. The channel layer has a doping concentration of 1×1015 cm−3 to 1×1021 cm−3.

公开(公告)号：US20220262599A1

公开(公告)日：2022-08-18

申请号：US17470337

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunbae KIM ,  Hyunjae LEE ,  Youngdo KIM ,  Hyejin KIM ,  Sangki NAM ,  Chanhee PARK ,  Minho JUNG

IPC: H01J37/32

Abstract: A variable frequency and non-sinusoidal power generator includes a pulse module circuit, a slope module circuit, and first and second cooling systems. The pulse module circuit and the slope module circuit includes control switches, and generates at least one of a output currents and a output voltages by selectively turning on/off the control switches based on control signals. The first and second cooling systems are disposed at first and second sides of the control switches. A bias power having a variable frequency and a non-sinusoidal waveform is generated based on the control signals, at least one of the output currents and the output voltages.

公开(公告)号：US20220140944A1

公开(公告)日：2022-05-05

申请号：US17433152

申请日：2020-02-21

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Min JANG ,  Sanghyo KIM ,  Hyunjae LEE ,  Hyosang JU ,  Jonghwan KIM ,  Hyuntack LIM ,  Hongsil JEONG

IPC: H04L1/00 ,  H04L1/20

Abstract: The present disclosure relates to a 5th (5G) generation) or pre-5G communication system for supporting a higher data transmission rate beyond a 4th (4G) generation communication system such as long term evolution (LTE). The present disclosure relates to false alarm detection of detecting in a wireless communication system, and an operating method of a receiving node may include receiving a signal from a transmitting node, obtaining a plurality of decoding paths by decoding bits contained in the received signal, and determining whether the decoding is successful based on a detection metric determined based on values representing path metrics of the plurality of the decoding paths.

公开(公告)号：US20210281279A1

公开(公告)日：2021-09-09

申请号：US17277041

申请日：2019-07-23

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Min JANG ,  Sanghyo KIM ,  Hyunjae LEE ,  Hyosang JU ,  Jonghwan KIM ,  Hongsil JEONG

IPC: H03M13/11 ,  H03M13/13 ,  H03M13/09 ,  H03M13/00

Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a higher data transfer rate beyond a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure relates to encoding and decoding using a polar code in a wireless communication system. A method for operation of a first device in a wireless communication system may comprise the steps of: among sub-blocks including at least one node, identifying at least one inactive sub-block to deactivate the node operation in the sub-blocks; encoding data by using a construction matrix determined on the basis of the at least one inactive sub-block; and transmitting the encoded data to a second device.