公开(公告)号：US09210659B2

公开(公告)日：2015-12-08

申请号：US13902148

申请日：2013-05-24

Applicant: Samsung Electronics Co. Ltd.

Inventor： Taehwan Kim

IPC: H04M1/00 ,  H04W52/02

CPC classification number: H04W52/0225 ,  Y02D70/164

Abstract: A method and an apparatus for controlling a dormancy mode of the portable terminal by minimizing the dormancy mode entry delay of the display in power-off state are provided. The method includes starting, when the application processor and the communication processor stop data communication in display power-off state, a dormancy mode timer, checking, when the dormancy mode timer expires, a dormancy mode flag indicating communication channel state, and entering, when the dormancy mode flag indicates a communication channel connection release state, the dormancy mode, wherein the dormancy mode timer counts a number of segments constituting a maximum standby time for entering the dormancy mode.

Abstract translation: 提供了一种通过最小化断电状态下的显示器的休眠模式进入延迟来控制便携式终端的休眠模式的方法和装置。 该方法包括当应用处理器和通信处理器在显示器断电状态下停止数据通信时，启动休眠模式定时器，当休眠模式定时器期满时，检查指示通信信道状态的休眠模式标志，并且进入 休眠模式标志指示通信信道连接释放状态，休眠模式，其中休眠模式定时器对构成进入休眠模式的最大待机时间的段数进行计数。

公开(公告)号：US20250015049A1

公开(公告)日：2025-01-09

申请号：US18412447

申请日：2024-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo Park ,  Sunggu Kang ,  Jae Choon Kim ,  Taehwan Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package includes a redistribution line structure that has a redistribution line layer. A first semiconductor chip is disposed above the redistribution line structure and includes a first region with a first thickness and a second region with a second thickness that is less than the first thickness. A sub-semiconductor package includes a second semiconductor chip and is disposed above the second region of the first semiconductor chip. A silicon through via penetrates the second region of the first semiconductor chip and electrically connects the sub-semiconductor package with the redistribution line structure. A sealant seals at least a portion of each of the first semiconductor chip and the sub-semiconductor package. The sub-semiconductor package is disposed within the second region of the first semiconductor chip.

公开(公告)号：US12142544B2

公开(公告)日：2024-11-12

申请号：US17734700

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwan Kim ,  Young-Deuk Kim ,  Jae Choon Kim ,  Kyung Suk Oh ,  Eungchang Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

公开(公告)号：US11483512B2

公开(公告)日：2022-10-25

申请号：US17119329

申请日：2020-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwan Kim ,  Sungjin Son ,  Seungjin Park ,  Kwangsub Byun ,  Junghwan Choi ,  Byungkwon Kang ,  Seokjae Lee

IPC: H04N5/445 ,  H04N21/431

Abstract: Provided are a display apparatus and an operation method thereof for preventing image flicker when displaying mixed images: generating a first image corresponding to video content on a first plane, generating, on a second plane, a second image, outputting a mixed image that is a mixture of the first image and the second image, generating a third image on a third plane corresponding to the mixed image, and displaying the third image based on removal of the first image from the display.

公开(公告)号：US09915681B2

公开(公告)日：2018-03-13

申请号：US14955545

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghoon Jang ,  Minsuk Choi ,  Byungho Choi ,  Taehwan Kim

IPC: G01R1/067

CPC classification number: G01R1/06722

Abstract: A semiconductor test apparatus includes a pogo pin that is provided on a board and is in contact with an inspected object. The pogo pin includes a barrel fixedly disposed on the board, a plunger movably coupled to the barrel, and a conduction film covering the pogo pin. The conduction film contacts a portion of the plunger to be electrically connected to the plunger while being electrically insulated from the barrel.

公开(公告)号：US20240404955A1

公开(公告)日：2024-12-05

申请号：US18800320

申请日：2024-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Taehwan Kim ,  Hyunjung Song ,  Hyoeun Kim ,  Wonil Lee ,  Sanguk Han

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package includes a redistribution structure, a lower semiconductor device arranged on the redistribution structure and including first through electrodes each having a first horizontal width, a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction and including second through electrodes each having a second horizontal width greater than the first horizontal width, a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate, and an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the first and second through electrodes. A plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device, and the first horizontal width is about 1 μm to about 7 μm and the second horizontal width is about 10 μm to about 20 μm.

公开(公告)号：US12108132B2

公开(公告)日：2024-10-01

申请号：US17727296

申请日：2022-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeheung Park ,  Kwangseok Byon ,  Hwajoong Jung ,  Bongchan Kim ,  Taehwan Kim ,  Hyungjin Rho ,  Kihuk Lee

IPC: H04N23/55 ,  G02B27/64 ,  H04N23/54

CPC classification number: H04N23/55 ,  G02B27/646 ,  H04N23/54

Abstract: An electronic device including a camera module is provided. The camera module includes a lens assembly including a lens, a lens holder in which the lens assembly is fixedly disposed, a sensor carrier that includes an image sensor at least partially aligned with an optical axis of the lens and a circuit board electrically connected with the image sensor and that moves in a first axial direction perpendicular to the optical axis and a second axial direction perpendicular to the optical axis and the first axial direction, a fixed substrate adjacent to the sensor carrier and fixed in a specified position, and a connecting member that extends from the circuit board to the fixed substrate and that extends to surround at least three interconnected edges of the circuit board when viewed in a direction of the optical axis.

公开(公告)号：US20240079366A1

公开(公告)日：2024-03-07

申请号：US18454217

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonggyu Lee ,  Jaechoon Kim ,  Taehwan Kim ,  Hwanjoo Park

IPC: H01L23/00 ,  H01L23/36 ,  H01L25/065

CPC classification number: H01L24/33 ,  H01L23/36 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/065 ,  H01L2924/16235 ,  H01L2924/1631 ,  H01L2924/1632 ,  H01L2924/165

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate and having a first surface facing the package substrate and a second surface, opposite to the first surface, an encapsulant disposed on the package substrate and on a side surface of the semiconductor chip, a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip, a bonding enhancing layer on the second surface of the semiconductor chip, a thermal interface material layer on the bonding enhancing layer and in a gap between the bonding enhancing layer and the heat dissipation member, wherein the thermal interface material layer includes liquid metal, and a porous barrier structure formed of a metal material and surrounding the bonding enhancing layer and the thermal interface material layer.

公开(公告)号：US20240055339A1

公开(公告)日：2024-02-15

申请号：US18229039

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo Park ,  Sunggu Kang ,  Jaechoon Kim ,  Taehwan Kim ,  Sungho Mun ,  Jonggyu Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/3675 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2924/182

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor package on the first redistribution structure, the first semiconductor package including a first semiconductor chip which includes a first device layer and a first semiconductor substrate including a through electrode, a second semiconductor chip which is on the first semiconductor chip and includes a second device layer and a second semiconductor substrate, and a molding member surrounding the first semiconductor chip, a second redistribution structure on an upper surface of the molding member, and a second semiconductor package on the second redistribution structure, the second semiconductor package including a third semiconductor chip, wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction, and an upper surface of the second semiconductor chip is higher than the upper surface of the molding member.

公开(公告)号：US20230092410A1

公开(公告)日：2023-03-23

申请号：US17736500

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan Kim ,  Kyungsuk Oh ,  Jaechoon Kim

IPC: H01L23/367 ,  H01L25/04 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including first through electrodes and having a first hot zone in which the first through electrodes are disposed; a heat redistribution chip disposed on the first semiconductor chip, having a cool zone overlapping the first hot zone in a stacking direction with respect to the first semiconductor chip, and including first heat redistribution through electrodes disposed outside of an outer boundary of the cool zone and electrically connected to the first through electrodes, respectively; a second semiconductor chip disposed on the heat redistribution chip, having a second hot zone overlapping the cool zone in the stacking direction, and including second through electrodes disposed in the second hot zone and electrically connected to the first heat redistribution through electrodes, respectively; and a first thermal barrier layer disposed between the first hot zone and the cool zone, wherein the first through electrodes are electrically connected to the second through electrodes by bypassing the cool zone via the first heat redistribution through electrodes.