公开(公告)号：US20240170366A1

公开(公告)日：2024-05-23

申请号：US18512640

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggyu Lee ,  Youngsuk Nam ,  Seokkan Ki ,  Jaechoon Kim ,  Taehwan Kim

IPC: H01L23/427 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/4275 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/065 ,  H01L2924/1611 ,  H01L2924/186 ,  H01L2924/20102

Abstract: Provided is a semiconductor package including a circuit board, a semiconductor chip on the circuit board, a heat dissipation member adjacent to the semiconductor chip, and a heat transmission member between the semiconductor chip and the heat dissipation member, the heat transmission member including a resin insulating body and phase change metal particles connected to each other in the resin insulating body, wherein the phase change metal particles connect the semiconductor chip and the heat dissipation member, the phase change metal particles being configured to transmit heat generated by the semiconductor chip to the heat dissipation member.

公开(公告)号：US12237268B2

公开(公告)日：2025-02-25

申请号：US18660550

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US11935812B2

公开(公告)日：2024-03-19

申请号：US17209974

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd. ,  UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY

Inventor： Seunggeol Ryu ,  Seokkan Ki ,  Youngsuk Nam ,  Jaechoon Kim ,  Bangweon Lee ,  Seungtae Hwang

IPC: H01L23/373 ,  H01L23/473

CPC classification number: H01L23/3736 ,  H01L23/473

Abstract: A semiconductor package may include a package substrate, a semiconductor chip on the package substrate, a heat dissipation member on the semiconductor chip, and a first thermal interface material coated on an upper surface of the semiconductor chip to bond the semiconductor chip and the heat dissipation member. The first thermal interface material may include a liquid metal and fine particles disposed inside the liquid metal. The fine particles may have no oxide layer on a surface thereof. A volume percentage of the fine particles in the liquid metal including the fine particles therein may be about 1% to about 5%. A thermal conductivity of the liquid metal including the fine particles therein may be equal to or more than about 40 W/m·K.

公开(公告)号：US08988115B2

公开(公告)日：2015-03-24

申请号：US13830651

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  SangWook Ju ,  Eunseok Cho

IPC: H01L35/00 ,  H03K3/011 ,  G06F1/20 ,  G06F1/32 ,  G06F11/30

CPC classification number: H03K3/011 ,  G06F1/203 ,  G06F1/206 ,  G06F1/324 ,  G06F11/3058 ,  Y02D10/126

Abstract: A method for controlling a temperature of an electronic device which includes a semiconductor chip is provided. The temperature control method includes measuring a temperature of a measurement point using the electronic device, comparing the temperature of the measurement point with a target temperature varying according to a period of time when the semiconductor chip operates using the electronic device, and decreasing a clock frequency of the semiconductor chip using the electronic device when the temperature of the measurement point is higher than the target temperature.

Abstract translation: 提供了一种用于控制包括半导体芯片的电子设备的温度的方法。 温度控制方法包括使用电子装置测量测量点的温度，将测量点的温度与根据半导体芯片使用电子设备操作的时间段变化的目标温度进行比较，并且降低时钟频率 当测量点的温度高于目标温度时，使用电子器件的半导体芯片。

公开(公告)号：US20240079366A1

公开(公告)日：2024-03-07

申请号：US18454217

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonggyu Lee ,  Jaechoon Kim ,  Taehwan Kim ,  Hwanjoo Park

IPC: H01L23/00 ,  H01L23/36 ,  H01L25/065

CPC classification number: H01L24/33 ,  H01L23/36 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/065 ,  H01L2924/16235 ,  H01L2924/1631 ,  H01L2924/1632 ,  H01L2924/165

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate and having a first surface facing the package substrate and a second surface, opposite to the first surface, an encapsulant disposed on the package substrate and on a side surface of the semiconductor chip, a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip, a bonding enhancing layer on the second surface of the semiconductor chip, a thermal interface material layer on the bonding enhancing layer and in a gap between the bonding enhancing layer and the heat dissipation member, wherein the thermal interface material layer includes liquid metal, and a porous barrier structure formed of a metal material and surrounding the bonding enhancing layer and the thermal interface material layer.

公开(公告)号：US20240055339A1

公开(公告)日：2024-02-15

申请号：US18229039

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo Park ,  Sunggu Kang ,  Jaechoon Kim ,  Taehwan Kim ,  Sungho Mun ,  Jonggyu Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/3675 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2924/182

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor package on the first redistribution structure, the first semiconductor package including a first semiconductor chip which includes a first device layer and a first semiconductor substrate including a through electrode, a second semiconductor chip which is on the first semiconductor chip and includes a second device layer and a second semiconductor substrate, and a molding member surrounding the first semiconductor chip, a second redistribution structure on an upper surface of the molding member, and a second semiconductor package on the second redistribution structure, the second semiconductor package including a third semiconductor chip, wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction, and an upper surface of the second semiconductor chip is higher than the upper surface of the molding member.

公开(公告)号：US20230092410A1

公开(公告)日：2023-03-23

申请号：US17736500

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan Kim ,  Kyungsuk Oh ,  Jaechoon Kim

IPC: H01L23/367 ,  H01L25/04 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including first through electrodes and having a first hot zone in which the first through electrodes are disposed; a heat redistribution chip disposed on the first semiconductor chip, having a cool zone overlapping the first hot zone in a stacking direction with respect to the first semiconductor chip, and including first heat redistribution through electrodes disposed outside of an outer boundary of the cool zone and electrically connected to the first through electrodes, respectively; a second semiconductor chip disposed on the heat redistribution chip, having a second hot zone overlapping the cool zone in the stacking direction, and including second through electrodes disposed in the second hot zone and electrically connected to the first heat redistribution through electrodes, respectively; and a first thermal barrier layer disposed between the first hot zone and the cool zone, wherein the first through electrodes are electrically connected to the second through electrodes by bypassing the cool zone via the first heat redistribution through electrodes.

公开(公告)号：US20230063886A1

公开(公告)日：2023-03-02

申请号：US17844395

申请日：2022-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun Jo ,  Youngdeuk Kim ,  Jaechoon Kim ,  Taehwan Kim ,  Kyungsuk Oh

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, and a plurality of third semiconductor chips sequentially stacked on the second semiconductor chip, in which a horizontal width of each of the first semiconductor chip and the second semiconductor chip is greater than a horizontal width of each of the plurality of third semiconductor chips, and the first semiconductor chip and the second semiconductor chip are connected to each other through direct contact of a bonding pad.

公开(公告)号：US20220130761A1

公开(公告)日：2022-04-28

申请号：US17374713

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L23/36 ,  H01L23/00

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US20250096061A1

公开(公告)日：2025-03-20

申请号：US18964984

申请日：2024-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan Kim ,  Kyungsuk Oh ,  Jaechoon Kim

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/04

Abstract: A semiconductor package includes a first semiconductor chip including first through electrodes and having a first hot zone in which the first through electrodes are disposed; a heat redistribution chip disposed on the first semiconductor chip, having a cool zone overlapping the first hot zone in a stacking direction with respect to the first semiconductor chip, and including first heat redistribution through electrodes disposed outside of an outer boundary of the cool zone and electrically connected to the first through electrodes, respectively; a second semiconductor chip disposed on the heat redistribution chip, having a second hot zone overlapping the cool zone in the stacking direction, and including second through electrodes disposed in the second hot zone and electrically connected to the first heat redistribution through electrodes, respectively; and a first thermal barrier layer disposed between the first hot zone and the cool zone, wherein the first through electrodes are electrically connected to the second through electrodes by bypassing the cool zone via the first heat redistribution through electrodes.