公开(公告)号：US11321177B2

公开(公告)日：2022-05-03

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C11/4091 ,  G11C11/408

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20200174882A1

公开(公告)日：2020-06-04

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/00 ,  G11C11/406

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US09917462B2

公开(公告)日：2018-03-13

申请号：US14621782

申请日：2015-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chiseon Won ,  Yongjun Yu ,  Jongkyu Lee ,  Siyoul Choi ,  Hyunseok Kim

IPC: H02J7/00 ,  G06F1/26

CPC classification number: H02J7/007 ,  G06F1/266 ,  H02J7/008

Abstract: A method is provided comprising: detecting an electrical connection between a first device having a first battery and a second device having a second battery; receiving an indication of a residual power of the second battery; displaying, by the first device, a power sharing interface based on the indication of the residual power of the second battery; detecting an input to the interface specifying a threshold amount of power; transmitting power from the first battery to the second device until the threshold amount of power is transmitted.