-
11.发明申请公开(公告)号：US20220165562A1
公开(公告)日：2022-05-26
申请号：US17650710
申请日：2022-02-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho-Young Kim , Chae Lyoung Kim , Tae-Hong Kim , Youngjun Kim , Boun Yoon , Sol Han , Joonoh Kim
Abstract: A cleaning apparatus includes a gas supply line and a cleaning liquid supply line. A nozzle is connected to the gas and the cleaning liquid supply lines. The nozzle applies the cleaning liquid to a substrate. A gas entrance port at a top of a body of the nozzle is connected to the gas supply line. A first cleaning liquid entrance port is disposed on a sidewall of the nozzle body and is connected to the cleaning liquid supply line. A fluid injection port is disposed at a bottom of the nozzle body and discharges both the gas and the cleaning liquid. An internal passage of the nozzle body connects each of the gas entrance port and the first cleaning liquid entrance port to the fluid injection port. The fluid injection port has a diameter that is greater than a diameter of the first cleaning liquid entrance port.
-
公开(公告)号：US11183500B2
公开(公告)日：2021-11-23
申请号：US16826655
申请日：2020-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoju Song , Seokhyun Kim , Youngjun Kim , Jinhyung Park , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC: H01L27/108
Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.
-
公开(公告)号：US12183803B2
公开(公告)日：2024-12-31
申请号：US17747238
申请日：2022-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaejin Lee , Youngjun Kim , Hunyoung Bark , Taekyung Yoon , Eunok Lee
Abstract: A gate structure includes a first gate electrode including a metal, a gate barrier pattern on the first gate electrode and including a metal nitride, and a second gate electrode on the gate barrier pattern. The gate structure is buried in an upper portion of a substrate. The gate barrier pattern has a flat upper surface and an uneven lower surface.
-
公开(公告)号：US12199364B2
公开(公告)日：2025-01-14
申请号：US17927837
申请日：2021-06-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junsig Kum , Hyunjin Kim , Youngjun Kim , Yoongeon Kim , Seungho Choi
IPC: H01Q9/04 , H01Q1/38 , H01Q9/40 , H04B7/0413
Abstract: The present disclosure provides a surface-mountable antenna structure that is applicable to a broadband massive multi-input multi-output (MIMO) unit (MMU) in a wireless communication system. An antenna structure according to an embodiment of the present disclosure comprises: a printed circuit board including a first ground port, a second ground port, and a first feeding port; a first antenna electrically connected to the first ground port; a second antenna electrically connected to the second ground port; and a first feeding plate including a first bending part electromagnetically coupled to the first antenna, a second bending part electromagnetically coupled to the second antenna, and a third bending part electrically connected to the first feeding port.
-
Patent Agency Ranking
公开(公告)号：US11844207B2
公开(公告)日：2023-12-12
申请号：US17579919
申请日：2022-01-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeonil Lee , Youngjun Kim , Jinbum Kim
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/0335 , H10B12/37 , H10B12/482
Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.
-
公开(公告)号：US11561518B2
公开(公告)日：2023-01-24
申请号：US17317572
申请日：2021-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaewook Kim , Youngjun Kim , Doheum Park , Yeongtae Shin
Abstract: An electronic apparatus and a control method thereof are provided. The electronic apparatus may include an interface; and a processor configured to obtain, via the interface, information related to values, which occur in time series, of a plurality of factors regarding a prediction object, identify, based on the information related to the values of the plurality of factors, at least one factor, from among the plurality of factors, having a time series change of values that corresponds to a time series change of reference values of the prediction object, and output information related to a predicted value of the prediction object based on the time series change of the values of the at least one factor.
-
公开(公告)号：US20220254787A1
公开(公告)日：2022-08-11
申请号：US17667697
申请日：2022-02-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Kim , Seokhyun Kim , Jinhyung Park , Hoju Song , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC: H01L27/108
Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
-
公开(公告)号：US11251188B2
公开(公告)日：2022-02-15
申请号：US16990305
申请日：2020-08-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok-Hyun Kim , Joon Young Kang , Youngjun Kim , Jinhyung Park , Ho-Ju Song , Sang-Jun Lee , Hyeran Lee , Bong-Soo Kim , Sungwoo Kim
IPC: H01L27/088 , H01L21/00 , H01L27/108
Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.
-
公开(公告)号：US20210035983A1
公开(公告)日：2021-02-04
申请号：US16826655
申请日：2020-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoju Song , Seokhyun Kim , Youngjun Kim , Jinhyung Park , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC: H01L27/108
Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.022 seconds)
