公开(公告)号：US10803912B2

公开(公告)日：2020-10-13

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

公开(公告)号：US20200273512A1

公开(公告)日：2020-08-27

申请号：US16281699

申请日：2019-02-21

Applicant: SanDisk Technologies LLC

Inventor： Christopher J. Petti ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yoocharn Jeon

IPC: G11C11/16 ,  H01L27/22

Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

公开(公告)号：US10692570B2

公开(公告)日：2020-06-23

申请号：US16195175

申请日：2018-11-19

Applicant: SanDisk Technologies LLC

Inventor： Ali Al-Shamma

IPC: G11C11/56 ,  G11C16/26 ,  G06F17/16 ,  G11C16/10 ,  G06N3/02 ,  G11C16/08

Abstract: Various examples for accelerating multiplication operations are presented, which can be employed in neural network operations, among other applications. In one example, a circuit comprises a non-volatile memory cell, and an input circuit coupled to a gate terminal of the non-volatile memory cell. The input circuit is configured to ramp a control voltage applied to the gate terminal at a ramp rate representing a multiplicand value. An output circuit coupled to an output terminal of the non-volatile memory cell and is configured to generate an output pulse based on the control voltage satisfying a threshold voltage of the non-volatile memory cell, where the output pulse has a duration comprising the multiplicand value multiplied by a multiplier value represented by the threshold voltage.

公开(公告)号：US20200020393A1

公开(公告)日：2020-01-16

申请号：US16195175

申请日：2018-11-19

Applicant: SanDisk Technologies LLC

Inventor： Ali Al-Shamma

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G06N3/02 ,  G06F17/16

Abstract: Various examples for accelerating multiplication operations are presented, which can be employed in neural network operations, among other applications. In one example, a circuit comprises a non-volatile memory cell, and an input circuit coupled to a gate terminal of the non-volatile memory cell. The input circuit is configured to ramp a control voltage applied to the gate terminal at a ramp rate representing a multiplicand value. An output circuit coupled to an output terminal of the non-volatile memory cell and is configured to generate an output pulse based on the control voltage satisfying a threshold voltage of the non-volatile memory cell, where the output pulse has a duration comprising the multiplicand value multiplied by a multiplier value represented by the threshold voltage.

公开(公告)号：US10170162B2

公开(公告)日：2019-01-01

申请号：US15602889

申请日：2017-05-23

Applicant: SanDisk Technologies LLC

Inventor： Ali Al-Shamma ,  Tz-yi Liu

IPC: G11C7/02 ,  G11C7/22 ,  G11C7/06 ,  G11C7/10

Abstract: A calibration circuit coupled to a sense amplifier circuit may be configured to determine a response time of the sense amplifier circuit relative to a pulse sequence. Based on the determined response time, the calibration circuit may be configured to set a level of a biasing current to a desired level in order to control the response time of the sense amplifier circuit.

公开(公告)号：US20170117035A1

公开(公告)日：2017-04-27

申请号：US15299338

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nima Mokhlesi ,  Ali Al-Shamma

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C5/14 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.