公开(公告)号：USRE47226E1

公开(公告)日：2019-02-05

申请号：US14231564

申请日：2014-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nima Mokhlesi ,  Henry Chin

IPC: G11C16/04 ,  G11C11/56 ,  G11C29/00

Abstract: A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

公开(公告)号：USRE46995E1

公开(公告)日：2018-08-14

申请号：US14231561

申请日：2014-03-31

Applicant: SanDisk Technologies LLC

Inventor： Nima Mokhlesi

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/349 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641

Abstract: A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block (target block) of multi-state data using a multi-state programming process, where the target block has been previously programmed with binary data X times (or less than X times).

公开(公告)号：US09715924B2

公开(公告)日：2017-07-25

申请号：US15299338

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nima Mokhlesi ,  Ali Al-Shamma

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C5/14 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.

公开(公告)号：US20170117037A1

公开(公告)日：2017-04-27

申请号：US15299372

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nima Mokhlesi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/3481 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/0403 ,  H01L27/11582 ,  H01L28/00

Abstract: A non-volatile storage system dedicates a subset of blocks to be used for shorting source lines to bit lines at periodic positions along the bit lines during certain memory operations.

公开(公告)号：US20170117036A1

公开(公告)日：2017-04-27

申请号：US15299357

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ali Al-Shamma ,  Nima Mokhlesi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/3481 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/0403 ,  H01L27/11582 ,  H01L28/00

Abstract: A non-volatile storage system includes a plurality of non-volatile memory cells configured to form a monolithic three dimensional memory structure, a plurality of bit lines connected to the memory cells, a plurality of source lines connected to the memory cells, a plurality of bit line drivers connected to the bit lines and a plurality of source line drivers connected to the source lines and the bit lines. The source line drivers apply voltages to the source lines based on bit line voltages.

公开(公告)号：US20170076802A1

公开(公告)日：2017-03-16

申请号：US14853733

申请日：2015-09-14

Applicant: SanDisk Technologies, LLC.

Inventor： Nima Mokhlesi

IPC: G11C16/14 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5624

Abstract: A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.

Abstract translation: 使用一系列编程脉冲，其中单个脉冲由脉冲数标识，用于并行编程存储器单元的页面。 在接收到脉冲之后，验证的存储器单元被确认以确定它们是否被编程到它们各自的目标状态。 已经验证的存储器单元被禁止进一步编程，而未被验证的那些存储器单元将被随后的编程脉冲进一步编程。 脉冲，验证和禁止继续，直到页面的所有存储单元已经被程序验证。 验证中使用的每个验证级别都是目标状态和脉冲数的函数。 这允许调整验证电平以补偿感测变化，包括在编程过程中由于源线负载变化引起的变化。

公开(公告)号：US10157681B2

公开(公告)日：2018-12-18

申请号：US14853733

申请日：2015-09-14

Applicant: SanDisk Technologies LLC

Inventor： Nima Mokhlesi

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.

公开(公告)号：US09911488B2

公开(公告)日：2018-03-06

申请号：US15299372

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nima Mokhlesi

IPC: G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/3481 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/0403 ,  H01L27/11582 ,  H01L28/00

Abstract: A non-volatile storage system dedicates a subset of blocks to be used for shorting source lines to bit lines at periodic positions along the bit lines during certain memory operations.

公开(公告)号：US20170117035A1

公开(公告)日：2017-04-27

申请号：US15299338

申请日：2016-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nima Mokhlesi ,  Ali Al-Shamma

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C5/14 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.