Abstract:
A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.
Abstract:
A circuit device includes a current supply circuit adapted to supply an oscillation current, an oscillation circuit having an oscillation transistor for a resonator, and adapted to drive the resonator using the oscillation transistor based on an oscillation current from the current supply circuit, and a control section adapted to control the current supply circuit. If the oscillation circuit is set to an overdrive mode, the oscillation circuit drives the resonator with a higher drive power than the drive power in a normal mode.
Abstract:
A circuit device includes an oscillation circuit configured to generate an oscillation signal, a first pre-driver disposed in a posterior stage of the oscillation circuit, a first output driver disposed in a posterior stage of the first pre-driver, a first regulator configured to supply a first regulated voltage to the first pre-driver, and a second regulator configured to supply a second regulated voltage to the first output driver, wherein the second regulator is shorter in transient response time than the first regulator.
Abstract:
A circuit device includes an oscillation circuit configured to oscillate a resonator to thereby generate an oscillation signal, a waveform shaping circuit to which the oscillation signal is input, and which is configured to output a clock signal obtained by performing waveform shaping on the oscillation signal, a first duty adjustment circuit configured to perform a duty adjustment of the clock signal, and an output buffer circuit configured to output a first output clock signal and a second output clock signal to an outside based on the clock signal. The output buffer circuit includes a second duty adjustment circuit configured to perform a duty adjustment of the second output clock signal.
Abstract:
A manufacturing method of an oscillator is a manufacturing method of an oscillator which includes a vibrator and a semiconductor circuit device including an oscillation part connected to the vibrator and a control part to switch an operation mode between a normal mode in which the oscillation part performs an oscillation operation and an inspection mode in which characteristics of the vibrator are inspected, and the manufacturing method includes preparing the semiconductor circuit device in which the operation mode is set to the inspection mode, connecting the semiconductor circuit device and the vibrator electrically, and inspecting the characteristics of the vibrator which is in a state electrically connected to the semiconductor circuit device.
Abstract:
An oscillation circuit includes a terminal XO which is connected to one end of a resonator, a terminal XI which is connected to the other end of the resonator, an oscillation unit which is electrically connected to the terminal XO and the terminal XI, a control voltage generation circuit, and a switch. The oscillation unit includes a variable capacitive element having one end which is connected to the terminal XO or the terminal XI. The switch controls electrical connection between the other end of the variable capacitive element and an output terminal of the control voltage generation circuit.
Abstract:
A circuit device includes: an output circuit including a waveform-shaping circuit of an oscillation signal and configured to output an output clock signal based on a clock signal subjected to waveform-shaping; a bias voltage output circuit configured to output a bias voltage of the oscillation signal input to the waveform-shaping circuit; a comparator configured to compare a DC voltage obtained by smoothing the clock signal subjected to the waveform-shaping with a reference voltage; a logic circuit configured to set an adjustment value of the bias voltage; and a storage circuit. In a test mode, the logic circuit changes the adjustment value to determine a set value of the adjustment value based on output of the comparator when the adjustment value is changed, and stores the determined set value in the storage circuit.
Abstract:
A circuit device includes a first oscillation circuit, a second oscillation circuit, a clock signal output circuit adapted to output a clock signal based on an output signal of the first oscillation circuit, and an output control circuit adapted to perform output control of the clock signal output circuit. The output control circuit includes a counter circuit adapted to perform a counting process based on an output signal of the second oscillation circuit, and the counter circuit outputs an output enable signal of the clock signal to the clock signal output circuit based on a result of the counting process.
Abstract:
A circuit device includes a first pad and a second pad that are disposed in a first pad disposition region along a first side; a third pad and a fourth pad that are disposed in a second pad disposition region along a second side which faces the first side; and a first to fourth electrostatic protection circuits that are disposed in a circuit disposition region between the first pad disposition region and the second pad disposition region and are connected to the first to fourth pads.
Abstract:
A circuit device includes an oscillation circuit, a clock signal output circuit that outputs a clock signal based on an output signal from the oscillation circuit, and an output control circuit. The output control circuit includes a counter circuit that performs a counting process on the basis of the output signal from the oscillation circuit, and a count enable signal generation circuit that outputs a count enable signal for the counter circuit. The counter circuit starts the counting process when the count enable signal becomes active, and outputs an output enable signal for the clock signal to the clock signal output circuit on the basis of a result of the counting process.