公开(公告)号：US11823754B2

公开(公告)日：2023-11-21

申请号：US18206702

申请日：2023-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/18 ,  G09G3/3266 ,  G09G3/36 ,  H01L27/12 ,  H01L29/786

CPC classification number: G11C19/184 ,  G09G3/3266 ,  G09G3/3677 ,  H01L27/1225 ,  H01L29/7869 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2340/0492

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

公开(公告)号：US11783906B2

公开(公告)日：2023-10-10

申请号：US17849770

申请日：2022-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/18 ,  G09G3/3266 ,  G09G3/36 ,  H01L29/786 ,  H01L27/12

CPC classification number: G11C19/184 ,  G09G3/3266 ,  G09G3/3677 ,  H01L27/1225 ,  H01L29/7869 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2340/0492

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

公开(公告)号：US11749685B2

公开(公告)日：2023-09-05

申请号：US17087801

申请日：2020-11-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hajime Kimura

IPC: G11C19/00 ,  H01L27/12 ,  G11C19/28 ,  G09G3/36 ,  G09G3/20 ,  H01L29/786

CPC classification number: H01L27/1225 ,  G09G3/20 ,  G09G3/3674 ,  G09G3/3677 ,  G11C19/28 ,  G11C19/287 ,  H01L27/124 ,  H01L29/7869 ,  G09G2310/0286

Abstract: An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

公开(公告)号：US11735133B2

公开(公告)日：2023-08-22

申请号：US17961062

申请日：2022-10-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  H01L23/528 ,  G02F1/1345 ,  G02F1/1362 ,  H01L29/786 ,  G11C19/28 ,  H01L27/12 ,  G02F1/136

CPC classification number: G09G3/3674 ,  G02F1/13454 ,  G02F1/136286 ,  G09G3/3677 ,  G11C19/28 ,  H01L23/528 ,  H01L29/786 ,  G02F1/13606 ,  G02F2201/124 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  H01L27/1214 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

公开(公告)号：US11688358B2

公开(公告)日：2023-06-27

申请号：US17979836

申请日：2022-11-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3648 ,  G09G3/2096 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/043

Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

公开(公告)号：US11663989B2

公开(公告)日：2023-05-30

申请号：US17848488

申请日：2022-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Ryo Arasawa

IPC: G09G3/36 ,  G11C19/18 ,  H01L27/12 ,  H01L49/02 ,  G09G3/3266 ,  G09G3/34

CPC classification number: G09G3/3677 ,  G11C19/184 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L28/40 ,  G09G3/3266 ,  G09G3/344 ,  G09G2300/0809 ,  G09G2310/0213 ,  G09G2310/0267

Abstract: It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.

公开(公告)号：US11545105B2

公开(公告)日：2023-01-03

申请号：US17153975

申请日：2021-01-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Atsushi Umezaki

IPC: G11C19/00 ,  G09G3/36 ,  H03K19/00 ,  H03K19/0185 ,  H03K17/687 ,  H01L27/12 ,  H01L27/02 ,  H01L29/786

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

公开(公告)号：US11455968B2

公开(公告)日：2022-09-27

申请号：US17190945

申请日：2021-03-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/28 ,  G09G3/36 ,  G11C19/18 ,  H01L27/12

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

公开(公告)号：US11373615B2

公开(公告)日：2022-06-28

申请号：US17070128

申请日：2020-10-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Ryo Arasawa

IPC: G09G3/36 ,  G11C19/18 ,  H01L27/12 ,  H01L49/02 ,  G09G3/3266 ,  G09G3/34

Abstract: It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.

公开(公告)号：US20220085072A1

公开(公告)日：2022-03-17

申请号：US17534577

申请日：2021-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  G09G3/36 ,  G09G3/20 ,  H01L21/84 ,  G02F1/1368 ,  H01L27/15 ,  G02F1/133 ,  G02F1/1362 ,  H01L27/32

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.