公开(公告)号：US12206370B2

公开(公告)日：2025-01-21

申请号：US17619669

申请日：2020-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Takayuki Ikeda ,  Kiyoshi Kato ,  Yuichi Yanagisawa ,  Shota Mizukami ,  Kazuki Tsuda

IPC: H03G3/30 ,  H01L29/786 ,  H03F1/02 ,  H03F3/195

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

公开(公告)号：US12087863B2

公开(公告)日：2024-09-10

申请号：US17615759

申请日：2020-05-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi Kunitake ,  Kazuaki Ohshima

IPC: H03H7/38 ,  H01L29/786 ,  H03F1/56 ,  H03H11/28

CPC classification number: H01L29/786 ,  H03F1/565 ,  H03H7/38 ,  H03H11/28

Abstract: A matching circuit which can handle a plurality of frequencies is provided. The matching circuit includes a transistor and an inductor. The matching circuit uses capacitance formed between a gate and a source/drain (referred to as capacitance Cgsd below) of the transistor as a condenser. The capacitance Cgsd changes with the voltage of the gate with respect to the source (referred to as voltage Vgs below). The transistor included in the matching circuit is an OS transistor including a metal oxide in a channel formation region. The OS transistor features larger variation in capacitance Cgsd with respect to the voltage Vgs than the MOSFET that uses silicon, which enables the matching circuit to handle alternating-current signals in a wide frequency range.

公开(公告)号：US11985827B2

公开(公告)日：2024-05-14

申请号：US17790517

申请日：2021-01-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi Godo ,  Hitoshi Kunitake ,  Kazuki Tsuda

IPC: H10B43/27 ,  G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/08 ,  H10B41/27

Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.

公开(公告)号：US11948945B2

公开(公告)日：2024-04-02

申请号：US17611689

申请日：2020-05-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuto Yakubo ,  Hitoshi Kunitake ,  Takayuki Ikeda

IPC: H01L27/12 ,  H03B5/12 ,  H04B1/40

CPC classification number: H01L27/1207 ,  H01L27/1225 ,  H03B5/12 ,  H01L27/124 ,  H04B1/40

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes an oscillation circuit including a first coil, a second coil, a first capacitor, a second capacitor, a first transistor, and a second transistor and a frequency correction circuit including a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a switching circuit. The switching circuit has a function of controlling a conduction state or a non-conduction state of the third transistor and the fourth transistor. The frequency correction circuit is provided above the oscillation circuit and has a function of adjusting an oscillation frequency of the oscillation circuit. The first transistor and the second transistor each include a semiconductor layer containing silicon in a channel formation region. The third transistor and the fourth transistor each include a semiconductor layer containing an oxide semiconductor in a channel formation region.

公开(公告)号：US11894040B2

公开(公告)日：2024-02-06

申请号：US17615867

申请日：2020-06-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki Ikeda ,  Hitoshi Kunitake

IPC: G11C11/405 ,  H01L27/12 ,  H01L29/786 ,  H03K3/012 ,  H10B12/00

CPC classification number: G11C11/405 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78648 ,  H03K3/012 ,  H10B12/00

Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes a plurality of constant current circuits each given a digital signal. The constant current circuits each include a first transistor to a third transistor. The first transistor has a function of making a first current corresponding to set analog potential flow therethrough. The second transistor has a function of controlling the first current flowing between a source and a drain of the first transistor, in response to the digital signal. The third transistor has a function of holding the analog potential supplied to a gate of the first transistor, by being turned off. The first transistor to the third transistor each include a semiconductor layer including an oxide semiconductor in a channel formation region.

公开(公告)号：US12225705B2

公开(公告)日：2025-02-11

申请号：US17419745

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Tatsuya Onuki ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC: H01L29/78 ,  G11C29/52 ,  H01L29/786 ,  H10B12/00

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

公开(公告)号：US20250015194A1

公开(公告)日：2025-01-09

申请号：US18763108

申请日：2024-07-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tsutomu Murakawa ,  Fumito Isaka ,  Hitoshi Kunitake ,  Yasuhiro Jinbo

IPC: H01L29/786 ,  H10B12/00

Abstract: A transistor that can be miniaturized is provided. The semiconductor device includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers. Over the first conductive layer including a depressed portion, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer which include a first opening portion overlapping with the depressed portion are provided in this order. The third insulating layer is in contact with at least the side surface of the second conductive layer in the first opening portion. The oxide semiconductor layer is in contact with the top surface of the third conductive layer and the bottom and side surfaces of the depressed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is on an inner side of the oxide semiconductor layer in the first opening portion. The fourth conductive layer is on an inner side of the fourth insulating layer in the first opening portion. In a cross-sectional view, the oxide semiconductor layer includes a region overlapping with the second conductive layer with the third insulating layer therebetween and overlapping with the fourth conductive layer with the fourth insulating layer therebetween.

公开(公告)号：US12142693B2

公开(公告)日：2024-11-12

申请号：US17642346

申请日：2020-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Yuichi Yanagisawa ,  Shota Mizukami ,  Kazuki Tsuda ,  Haruyuki Baba ,  Shunpei Yamazaki

IPC: H01L29/786

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor, a second conductor, a third oxide, a fourth oxide, and a second insulator over the second oxide; a third insulator over the first conductor, the second conductor, the third oxide, and the fourth oxide; a fourth insulator over the second insulator; and a third conductor over the fourth insulator. The second insulator is positioned between the first conductor and the second conductor. The third oxide is positioned between the first conductor and the second insulator. The fourth oxide is positioned between the second conductor and the second insulator. The thickness of the third oxide between the first conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm. The thickness of the fourth oxide between the second conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm.

公开(公告)号：US12082391B2

公开(公告)日：2024-09-03

申请号：US17762473

申请日：2020-09-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru Ohshita ,  Hitoshi Kunitake ,  Kazuki Tsuda

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H10B12/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

公开(公告)号：US12041762B2

公开(公告)日：2024-07-16

申请号：US17612873

申请日：2020-05-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuaki Ohshima ,  Hitoshi Kunitake ,  Takahiro Fukutome

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H10B12/00 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor.