公开(公告)号：US20220149045A1

公开(公告)日：2022-05-12

申请号：US17582092

申请日：2022-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/118 ,  H01L27/115 ,  H01L29/786

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20220139917A1

公开(公告)日：2022-05-05

申请号：US17414614

申请日：2019-11-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: H01L27/108 ,  H01L29/786

Abstract: A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.

公开(公告)号：US20220085073A1

公开(公告)日：2022-03-17

申请号：US17422312

申请日：2019-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Yuto YAKUBO ,  Yuki OKAMOTO ,  Seiya SAITO ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  G11C11/4091 ,  G11C11/4096

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.

公开(公告)号：US20220085020A1

公开(公告)日：2022-03-17

申请号：US17424621

申请日：2019-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.

公开(公告)号：US20210287732A1

公开(公告)日：2021-09-16

申请号：US17337552

申请日：2021-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shuhei MAEDA

IPC: G11C11/4094 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.

公开(公告)号：US20210273110A1

公开(公告)日：2021-09-02

申请号：US17261665

申请日：2019-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L27/108

Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

公开(公告)号：US20200342928A1

公开(公告)日：2020-10-29

申请号：US16962309

申请日：2020-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE

IPC: G11C11/408 ,  H01L27/108

Abstract: A novel storage device and a novel semiconductor device are provided.In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.

公开(公告)号：US20200185023A1

公开(公告)日：2020-06-11

申请号：US16640206

申请日：2018-08-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G11C11/4091 ,  H01L27/108 ,  G11C5/06 ,  G11C5/02

Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

公开(公告)号：US20190006397A1

公开(公告)日：2019-01-03

申请号：US16104397

申请日：2018-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L21/84 ,  H01L27/118 ,  H01L27/1156 ,  H01L27/11521 ,  H01L27/11517 ,  H01L27/11 ,  H01L27/108 ,  G11C16/26 ,  G11C16/04

Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

公开(公告)号：US20180138212A1

公开(公告)日：2018-05-17

申请号：US15811879

申请日：2017-11-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Yuta ENDO ,  Ryo TOKUMARU

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/108 ,  H01L29/10 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/443

CPC classification number: H01L27/1225 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/443 ,  H01L21/465 ,  H01L21/47573 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1255 ,  H01L27/1262 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device having favorable electric characteristics is provided. The semiconductor device includes a first transistor and second transistor. The first transistor includes a first conductor over a substrate; a first insulator thereover; a first oxide thereover; a second insulator over thereover; a second conductor including a side surface substantially aligned with a side surface of the second insulator and being over the second insulator; a third insulator including a side surface substantially aligned with a side surface of the second conductor and being over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the first oxide and the fourth insulator. The second transistor includes a third conductor; a fourth conductor at least part of which overlaps with the third conductor; and a second oxide between the third conductor and the fourth conductor. The third conductor and the fourth conductor are electrically connected to the first conductor.