公开(公告)号：US09543409B2

公开(公告)日：2017-01-10

申请号：US14855834

申请日：2015-09-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Christian Arvet ,  Sebastien Barnola ,  Sebastien Lagrasta ,  Nicolas Posseme

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/311 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/6656 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66628

Abstract: The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.

Abstract translation: 在晶体管栅极的侧面制造间隔物，包括形成覆盖栅极的介电层和围绕栅极的半导体材料层的外围区域的步骤，包括形成覆盖栅极和外围区域的表面层; 部分去除表层，构造成在外围区域完全除去表层，同时在侧面保留表层的残留部分; 并且相对于表层的残余部分的材料和相对于半导体材料的材料的电介质层的选择性蚀刻。