公开(公告)号：US12218231B2

公开(公告)日：2025-02-04

申请号：US17116465

申请日：2020-12-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando Iucolano ,  Alessandro Chini

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66

Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

公开(公告)号：US12165871B2

公开(公告)日：2024-12-10

申请号：US17083181

申请日：2020-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando Iucolano ,  Cristina Tringali

IPC: H01L29/778 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

公开(公告)号：US10411123B2

公开(公告)日：2019-09-10

申请号：US16036597

申请日：2018-07-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US20180342606A1

公开(公告)日：2018-11-29

申请号：US16036597

申请日：2018-07-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US20180108767A1

公开(公告)日：2018-04-19

申请号：US15832680

申请日：2017-12-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US20170141218A1

公开(公告)日：2017-05-18

申请号：US15156740

申请日：2016-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US12154967B2

公开(公告)日：2024-11-26

申请号：US16697051

申请日：2019-11-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Cristina Tringali

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

公开(公告)号：US11799025B2

公开(公告)日：2023-10-24

申请号：US16706539

申请日：2019-12-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Cristina Tringali

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/06 ,  H01L29/47 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L29/0649 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: An HEMT includes a semiconductor body, which includes a semiconductor heterostructure, and a conductive gate region. The gate region includes: a contact region, which is made of a first metal material and contacts the semiconductor body to form a Schottky junction; a barrier region, which is made of a second metal material and is set on the contact region; and a top region, which extends on the barrier region and is made of a third metal material, which has a resistivity lower than the resistivity of the first metal material. The HEMT moreover comprises a dielectric region, which includes at least one front dielectric subregion, which extends over the contact region, delimiting a front opening that gives out onto the contact region; and wherein the barrier region extends into the front opening and over at least part of the front dielectric subregion.

公开(公告)号：US11538922B2

公开(公告)日：2022-12-27

申请号：US17118439

申请日：2020-12-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando Iucolano

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/778 ,  H01L21/324 ,  H01L21/225 ,  H01L29/20

Abstract: A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

公开(公告)号：US11222969B2

公开(公告)日：2022-01-11

申请号：US16808311

申请日：2020-03-03

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02 ,  H01L29/205 ,  H01L29/417

Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.