公开(公告)号：US11699748B2

公开(公告)日：2023-07-11

申请号：US17322528

申请日：2021-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Giuseppe Greco ,  Fabrizio Roccaforte

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31 ,  H01L29/737 ,  H01L29/207 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/1087 ,  H01L29/207 ,  H01L29/41766 ,  H01L29/7378

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US11489068B2

公开(公告)日：2022-11-01

申请号：US17115459

申请日：2020-12-08

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando Iucolano ,  Alessandro Chini

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

公开(公告)号：US10050136B2

公开(公告)日：2018-08-14

申请号：US15371012

申请日：2016-12-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US20170345918A1

公开(公告)日：2017-11-30

申请号：US15371012

申请日：2016-12-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US12148823B2

公开(公告)日：2024-11-19

申请号：US17977971

申请日：2022-10-31

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando Iucolano ,  Alessandro Chini

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

公开(公告)号：US11862707B2

公开(公告)日：2024-01-02

申请号：US17396154

申请日：2021-08-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti ,  Alessandro Chini

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

公开(公告)号：US11316038B2

公开(公告)日：2022-04-26

申请号：US16688974

申请日：2019-11-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

公开(公告)号：US10896969B2

公开(公告)日：2021-01-19

申请号：US16254322

申请日：2019-01-22

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/778 ,  H01L21/324 ,  H01L21/225 ,  H01L29/20

Abstract: A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

公开(公告)号：US10522646B2

公开(公告)日：2019-12-31

申请号：US15159045

申请日：2016-05-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti ,  Alessandro Chini

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

公开(公告)号：US20180323296A1

公开(公告)日：2018-11-08

申请号：US16020807

申请日：2018-06-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L21/28 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.