公开(公告)号：US11862707B2

公开(公告)日：2024-01-02

申请号：US17396154

申请日：2021-08-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti ,  Alessandro Chini

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

公开(公告)号：US10522646B2

公开(公告)日：2019-12-31

申请号：US15159045

申请日：2016-05-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti ,  Alessandro Chini

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

公开(公告)号：US20180323296A1

公开(公告)日：2018-11-08

申请号：US16020807

申请日：2018-06-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L21/28 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US20180108767A1

公开(公告)日：2018-04-19

申请号：US15832680

申请日：2017-12-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US20170141218A1

公开(公告)日：2017-05-18

申请号：US15156740

申请日：2016-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US09508846B2

公开(公告)日：2016-11-29

申请号：US14662652

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Schillaci ,  Alfonso Patti ,  Paola Maria Ponzio

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7831

Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.

Abstract translation: 垂直型的MOS半导体器件具有：具有第一类导电性的功能层; 栅极结构，其形成在功能层上方并具有介电材料区域和电极区域; 具有第二类导电性的主体孔形成在功能层内，并被表面分离区分离; 源区，其具有第一类导电性并形成在体孔内。 每个栅极结构横向仅在一个相应的主体阱上方延伸，并且不与功能层的表面分离区域重叠。 该装置还可以具有：至少一个屏蔽结构，布置在表面分离区域上方的相邻门结构之间; 和/或具有第二类型导电性的至少一个掺杂控制区域，布置在表面分离区域内，两者都被设置在源极电位。

公开(公告)号：US11101363B2

公开(公告)日：2021-08-24

申请号：US16690035

申请日：2019-11-20

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti ,  Alessandro Chini

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

公开(公告)号：US10396192B2

公开(公告)日：2019-08-27

申请号：US16020807

申请日：2018-06-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L21/28 ,  H01L29/205

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US20170148906A1

公开(公告)日：2017-05-25

申请号：US15159127

申请日：2016-05-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L29/1045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

公开(公告)号：US20170141208A1

公开(公告)日：2017-05-18

申请号：US15159045

申请日：2016-05-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti ,  Alessandro Chini

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778

Abstract: A HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.