公开(公告)号：US10367068B2

公开(公告)日：2019-07-30

申请号：US15427656

申请日：2017-02-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/36 ,  H01L29/786

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

公开(公告)号：US09660034B1

公开(公告)日：2017-05-23

申请号：US15229746

申请日：2016-08-05

Applicant: STMicroelectronics SA

Inventor： Philippe Galy

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/1083 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/7838 ,  H01L29/78648

Abstract: An integrated circuit includes SOI-type MOS transistors on insulator, with a first well capable of being biased located under the insulator. The first wells are doped with a first conductivity type. Each first well includes, under the insulator of each transistor, a back gate region that is more heavily doped than the first well. The first wells are separated from each other by inclusion in in a second well that is also capable of being biased. The second well is doped with a second conductivity type.

公开(公告)号：US09455247B2

公开(公告)日：2016-09-27

申请号：US15087622

申请日：2016-03-31

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Jean Jimenez

IPC: H01L29/747 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0255 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module includes a thyristor having terminals and a gate, and a diode coupled in antiparallel to the terminals of the thyristor. Each module is sized to share a saturation current with neighboring modules when an electrostatic discharge current is received. A resistive network couples modules between two terminals. A triggering circuit includes a common triggering output that is coupled to the gate of the thyristor of each module and a common buried semiconductor layer contacts each module.

Abstract translation: 用于防止静电放电的半导体器件包括用于防止静电放电的多个模块。 每个模块包括具有端子和栅极的晶闸管和与晶闸管的端子反平行耦合的二极管。 当接收到静电放电电流时，每个模块的大小与相邻模块共享饱和电流。 电阻网络在两个终端之间耦合模块。 触发电路包括耦合到每个模块的晶闸管的栅极的公共触发输出，并且公共掩埋半导体层接触每个模块。

公开(公告)号：US20160218098A1

公开(公告)日：2016-07-28

申请号：US15087622

申请日：2016-03-31

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Jean Jimenez

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0255 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module includes a thyristor having terminals and a gate, and a diode coupled in antiparallel to the terminals of the thyristor. Each module is sized to share a saturation current with neighboring modules when an electrostatic discharge current is received. A resistive network couples modules between two terminals. A triggering circuit includes a common triggering output that is coupled to the gate of the thyristor of each module and a common buried semiconductor layer contacts each module.

Abstract translation: 用于防止静电放电的半导体器件包括用于防止静电放电的多个模块。 每个模块包括具有端子和栅极的晶闸管和与晶闸管的端子反平行耦合的二极管。 当接收到静电放电电流时，每个模块的大小与相邻模块共享饱和电流。 电阻网络在两个终端之间耦合模块。 触发电路包括耦合到每个模块的晶闸管的栅极的公共触发输出，并且公共掩埋半导体层接触每个模块。

公开(公告)号：US09230950B2

公开(公告)日：2016-01-05

申请号：US13859418

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Philippe Galy ,  Jean Jimenez

IPC: H01L27/02 ,  H01L21/77 ,  H01L27/12 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/43

CPC classification number: H01L27/0207 ,  H01L21/76264 ,  H01L21/77 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/435 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7825

Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract translation: 至少三个导电块设置在隔离区内; 并且它们中的至少两个被隔离区域的一部分相互分离和电容耦合。 它们中的至少两个是半导体，具有相反的导电性或相同类型的导电性，但是具有不同浓度的掺杂剂，并且这些掺杂物的两侧之间相互接触。 这些块在隔离区域内的相互排列，它们的导电类型及其掺杂剂的浓度形成至少一个电子模块。 一些块定义输入和输出块。

公开(公告)号：US12100752B2

公开(公告)日：2024-09-24

申请号：US17375285

申请日：2021-07-14

Applicant: STMicroelectronics SA

Inventor： Philippe Galy

IPC: H01L29/739 ,  H10B41/40 ,  H10B99/00

CPC classification number: H01L29/7391 ,  H10B41/40 ,  H10B99/00

Abstract: A cell includes a Z2-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

公开(公告)号：US11971313B2

公开(公告)日：2024-04-30

申请号：US17192411

申请日：2021-03-04

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Renan Lethiecq

IPC: G01K7/01 ,  G01K7/22 ,  G01K7/25 ,  G05F3/24 ,  H01C7/00 ,  H01C7/04 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78

CPC classification number: G01K7/01 ,  G01K7/015 ,  G01K7/22 ,  G01K7/226 ,  G01K7/25 ,  G05F3/245 ,  H01C7/008 ,  H01C7/04 ,  H01L27/1203 ,  H01L29/1095 ,  H01L29/7831

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

公开(公告)号：US10853038B2

公开(公告)日：2020-12-01

申请号：US16157464

申请日：2018-10-11

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06F7/58 ,  H03K3/012 ,  H03K3/84

Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.

公开(公告)号：US10795396B2

公开(公告)日：2020-10-06

申请号：US16572130

申请日：2019-09-16

Applicant: STMicroelectronics SA

Inventor： Renan Lethiecq ,  Philippe Galy

IPC: G01K7/25 ,  G05F3/24

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

公开(公告)号：US09947650B1

公开(公告)日：2018-04-17

申请号：US15497993

申请日：2017-04-26

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/45 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/456

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.