公开(公告)号：US20170116439A1

公开(公告)日：2017-04-27

申请号：US15137789

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Jimmy Fort ,  Clement Champeix ,  Jean-Max Dutertre ,  Nicolas Borrel

IPC: G06F21/86 ,  H03K5/153 ,  H03K5/24 ,  H01L23/00

CPC classification number: G06F21/86 ,  G09C1/00 ,  H01L23/576 ,  H03K5/153 ,  H03K5/24 ,  H04L9/004 ,  H04L2209/12

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

公开(公告)号：US11698651B2

公开(公告)日：2023-07-11

申请号：US17399674

申请日：2021-08-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Demange ,  Nicolas Borrel ,  Jimmy Fort

IPC: G05F1/56 ,  G06F21/75

CPC classification number: G05F1/56 ,  G06F21/755

Abstract: The present invention concerns an electronic circuit power supply device, configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node, a first branch of a current mirror conducting the third current; flow a fourth constant current through a third conductor connected to the node; consume a fifth current that is an image of the third current; and regulate a potential of the node by acting on a gate potential of a transistor electrically in series with a second branch of the current mirror.

公开(公告)号：US10770411B2

公开(公告)日：2020-09-08

申请号：US16382509

申请日：2019-04-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A method of protecting a first chip in a multi-chip stack includes determining an electrical characteristic of a conductive loop. The conductive loop extends over a top portion of the first chip. The conductive loop also extends through the first chip and within a top portion of a second chip. The top portion of the second chip is adjacent to a bottom portion of the first chip. The method further includes determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip.

公开(公告)号：US10691840B2

公开(公告)日：2020-06-23

申请号：US15137789

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Jimmy Fort ,  Clement Champeix ,  Jean-Max Dutertre ,  Nicolas Borrel

IPC: G06F21/86 ,  G09C1/00 ,  H04L9/00 ,  H01L23/00 ,  H03K5/153 ,  H03K5/24

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

公开(公告)号：US20190051723A1

公开(公告)日：2019-02-14

申请号：US16161785

申请日：2018-10-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel ,  Alexandre Sarafianos

IPC: H01L29/06 ,  H03K5/24 ,  H01L23/00 ,  G06F21/77 ,  G06F21/78 ,  H01L29/10 ,  H01L27/092 ,  H01L27/06 ,  G06F21/75 ,  G06F21/88 ,  G06F21/87 ,  H01L29/66

CPC classification number: H01L29/0623 ,  G06F21/75 ,  G06F21/77 ,  G06F21/78 ,  G06F21/87 ,  G06F21/88 ,  H01L21/823892 ,  H01L23/57 ,  H01L23/576 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/66181 ,  H03K5/24

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

公开(公告)号：US10141396B2

公开(公告)日：2018-11-27

申请号：US15444644

申请日：2017-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel ,  Alexandre Sarafianos

IPC: G06F21/78 ,  H01L29/06 ,  G06F21/88 ,  G06F21/77 ,  H01L27/06 ,  H01L29/10 ,  H03K5/24 ,  G06F21/75 ,  G06F21/87 ,  H01L23/00 ,  H01L29/66

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

公开(公告)号：US20180122753A1

公开(公告)日：2018-05-03

申请号：US15609783

申请日：2017-05-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/576 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: A device includes a first chip having a front side and a back side. A second chip is stacked with the first chip and located on the back side of the first chip. A first loop includes first and second through vias located in the first chip. Each through via has a first end on the front side of the first chip and a second end on the back side of the first chip. The first loop also includes a first track that connects the first ends of the first and second through vias is located in the first chip on the front side thereof and a second track that connects the second ends of the first and second through vias is located in the second chip. A detection circuit can detect an electrical characteristic of the first loop.

公开(公告)号：US20170092600A1

公开(公告)日：2017-03-30

申请号：US15072209

申请日：2016-03-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Nicolas Borrel

IPC: H01L23/00 ,  H03K17/687

CPC classification number: H01L23/576 ,  G01R31/2851 ,  G01R31/44 ,  G06F21/6245 ,  H01L22/34 ,  H01L23/647 ,  H03K17/687

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

公开(公告)号：US11829178B2

公开(公告)日：2023-11-28

申请号：US17399617

申请日：2021-08-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Demange ,  Nicolas Borrel ,  Jimmy Fort

IPC: G05F3/26 ,  G06F21/75

CPC classification number: G05F3/262 ,  G06F21/755

Abstract: An embodiment electronic circuit power supply device is configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node; regulate a potential of the node to a constant value by acting on the third current; flow a fourth constant current through a third conductor connected to the node; and consume a fifth current that is an image of the third current.

公开(公告)号：US20210405100A1

公开(公告)日：2021-12-30

申请号：US17322140

申请日：2021-05-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Mathieu Dumont ,  Nicolas Borrel ,  Mathieu Lisart

IPC: G01R29/08 ,  G06F21/55 ,  G06F21/75

Abstract: An embodiment integrated circuit includes a first electromagnetic pulse detection device that comprises a first loop antenna formed in an interconnection structure of the integrated circuit, a first end of the first antenna being connected to a first node of application of a power supply potential and a second end of the antenna being coupled to a second node of application of the power supply potential, and a first circuit connected to the second end of the first antenna and configured to output a first signal representative of a comparison of a first current in the first antenna with a first threshold.