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公开(公告)号:US10361164B2
公开(公告)日:2019-07-23
申请号:US15446472
申请日:2017-03-01
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Thomas Ordas , Alexandre Sarafianos , Fabrice Marinet , Stephane Chesnais
IPC: H01L23/00 , H01L23/62 , H01L27/02 , H01L23/522 , G06F21/75 , G06F21/87 , G06K19/073 , H01L23/528
Abstract: An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults.
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公开(公告)号:US10148421B2
公开(公告)日:2018-12-04
申请号:US15221749
申请日:2016-07-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Thomas Ordas , Alexandre Sarafianos , Stephane Chesnais , Fabrice Marinet
IPC: G06F21/00 , H04L9/00 , G06K19/073 , G09C1/00 , H04K3/00 , G06F1/04 , G06F21/72 , H01L23/528 , H03K3/84 , H03K5/01 , H03K5/00
Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.
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公开(公告)号:US20180253633A1
公开(公告)日:2018-09-06
申请号:US15801517
申请日:2017-11-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas
IPC: G06K19/073 , H03K3/42 , G05B19/042 , H01L21/56
Abstract: In some embodiments, an electronic chip includes a doped semiconductor substrate of a first conductivity type, and wells of the second conductivity type on the side of the front face of the chip, in and on which wells circuit elements are formed. One or more slabs of a second conductivity type are buried under the wells and are separated from the wells. The electronic chip also includes, for each buried slab, a biasable section of the second conductivity type, which extends from the front face of the substrate to the buried slab. A first MOS transistor with a channel of the first conductivity type is disposed in the upper portion of each section, where the first transistor is an element of a flip-flop. A circuit is used for detecting a change in the logic level of one of the flip-flops.
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公开(公告)号:US11824969B2
公开(公告)日:2023-11-21
申请号:US17537056
申请日:2021-11-29
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor: Thomas Ordas , Yanis Linge
CPC classification number: H04L9/0618 , G06F21/72 , H04L9/0625 , H04L9/0631 , H04L9/0662 , H04L2209/043 , H04L2209/08 , H04L2209/12
Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.
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公开(公告)号:US11258579B2
公开(公告)日:2022-02-22
申请号:US16281887
申请日:2019-02-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor: Daniele Fronte , Yanis Linge , Thomas Ordas
Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm based on a scrambled substitution table. For each set of one or more substitution operations of the cryptographic algorithm, the circuit performs a series of sets of one or more substitution operations of which: one is a real set of one or more substitution operations defined by the cryptographic algorithm, the real set of one or more substitution operations being based on input data modified by a real scrambling key; and one or more others are dummy sets of one or more substitution operations, each dummy set of one or more dummy substitution operations being based on input data modified by a different false scrambling key.
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16.
公开(公告)号:US20190147771A1
公开(公告)日:2019-05-16
申请号:US16186820
申请日:2018-11-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas , Yanis Linge
IPC: G09C1/00 , H03K19/003
Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.
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公开(公告)号:US20190122090A1
公开(公告)日:2019-04-25
申请号:US16227525
申请日:2018-12-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06K19/073 , G06F21/75 , G06F21/44 , H01L23/00
Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
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公开(公告)号:US10198683B2
公开(公告)日:2019-02-05
申请号:US15798553
申请日:2017-10-31
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06K19/073 , G06F21/75 , G06F21/44 , H01L23/00 , H03K19/173 , H03K17/693
Abstract: An electronic device randomly modifies a current profile of a logic circuit by using an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
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公开(公告)号:US20180005964A1
公开(公告)日:2018-01-04
申请号:US15446472
申请日:2017-03-01
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Thomas Ordas , Alexandre Sarafianos , Fabrice Marinet , Stephane Chesnais
IPC: H01L23/00 , H01L23/528 , H01L23/62 , H01L27/02
CPC classification number: H01L23/576 , G06F21/75 , G06F21/87 , G06K19/07327 , G06K19/07363 , H01L23/5227 , H01L23/528 , H01L23/62 , H01L27/0255
Abstract: An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults
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