公开(公告)号：US20230386565A1

公开(公告)日：2023-11-30

申请号：US18136507

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/74

CPC classification number: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/742

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

公开(公告)号：US20210081773A1

公开(公告)日：2021-03-18

申请号：US17023144

申请日：2020-09-16

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Manuj AYODHYAWASI ,  Thomas BOESCH ,  Surinder Pal SINGH

IPC: G06N3/063 ,  G06F1/08 ,  G06F1/324 ,  G06F9/50 ,  G06N3/08 ,  G06F1/3228 ,  G06F1/3296

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

公开(公告)号：US20240143239A1

公开(公告)日：2024-05-02

申请号：US18379373

申请日：2023-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Manuj AYODHYAWASI ,  Nitin CHAWLA

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0655

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

公开(公告)号：US20230410892A1

公开(公告)日：2023-12-21

申请号：US18137261

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Harsh RAWAT ,  Manuj AYODHYAWASI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4085

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

公开(公告)号：US20230386564A1

公开(公告)日：2023-11-30

申请号：US18137159

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Nitin CHAWLA ,  Promod KUMAR ,  Harsh RAWAT ,  Manuj AYODHYAWASI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

公开(公告)号：US20230012567A1

公开(公告)日：2023-01-19

申请号：US17844955

申请日：2022-06-21

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

公开(公告)号：US20210072894A1

公开(公告)日：2021-03-11

申请号：US17012501

申请日：2020-09-04

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20240177769A1

公开(公告)日：2024-05-30

申请号：US18522547

申请日：2023-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Promod KUMAR ,  Kedar Janardan DHORI ,  Harsh RAWAT ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C8/08

Abstract: A memory array includes memory cells arranged in rows and columns where each row includes a word line connected to memory cells of the row and each column includes a bit line connected to memory cells of the column. Each memory cell stores a bit of weight data for an in-memory computation operation. A row controller circuit coupled to the word lines through drive circuits is configured to simultaneously actuate multiple word lines during the in-memory computation operation. A column processing circuit includes a discharge time sensing circuit for each column that generates an analog signal indicative of a time taken during the in-memory computation operation to discharge the bit line from a precharge voltage to a threshold voltage. The analog signals are converted to digital signal and a computation circuitry performs digital signal processing calculations on the digital signals to generate a decision output for the in-memory computation operation.

公开(公告)号：US20240112748A1

公开(公告)日：2024-04-04

申请号：US18228118

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Tanuj KUMAR ,  Hitesh CHAWLA ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G11C29/12015 ,  G11C29/32 ,  G11C2029/1204

Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.

公开(公告)号：US20240071546A1

公开(公告)日：2024-02-29

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

CPC classification number: G11C29/1201 ,  G11C29/36 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/3602

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.