公开(公告)号：US20200343869A1

公开(公告)日：2020-10-29

申请号：US16829088

申请日：2020-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Nitin GUPTA ,  Prashutosh GUPTA

IPC: H03F3/45 ,  H03G1/00 ,  H03F1/22 ,  H03F1/32

Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

公开(公告)号：US20180006797A1

公开(公告)日：2018-01-04

申请号：US15703792

申请日：2017-09-13

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tapas NANDY ,  Nitin GUPTA

IPC: H04L7/00 ,  H04L5/00 ,  H04L7/033 ,  H04L7/02 ,  G06F1/10 ,  H04L1/00 ,  H04J3/06 ,  H04L7/027

CPC classification number: H04L7/0008 ,  G06F1/10 ,  H04J3/0685 ,  H04L1/0026 ,  H04L5/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L7/0337

Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

公开(公告)号：US20150002197A1

公开(公告)日：2015-01-01

申请号：US14046041

申请日：2013-10-04

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (CROLLES 2) SAS

Inventor： Kallol CHATTERJEE ,  Nitin AGARWAL ,  Junaid YOUSUF ,  Nitin GUPTA ,  Pierre DAUTRICHE

IPC: H03L7/095

CPC classification number: H03L7/095

Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

Abstract translation: 变频时钟发生器。 在方面中，时钟发生器包括下垂检测器电路，其被配置为监视对集成电路的电压供应。 如果电源电压低于特定阈值，则可以设置下降电压标志，使得频率锁定环路被触发到用于处理电源电压的电压下降的下降电压模式。 作为响应，通过将电流从电流控制信号吸收到振荡器来减小输入到产生系统时钟信号的振荡器的电流控制信号。 这将立即降低系统时钟频率。 当去除电流路径以吸收一些电流时，这种状态保持直到电压下降消散。

公开(公告)号：US20140300386A1

公开(公告)日：2014-10-09

申请号：US14231026

申请日：2014-03-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin JAIN ,  Nitin GUPTA

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters.

Abstract translation: 电平移位电路包括第一反相器，其包括具有相反导电类型的一对晶体管，第一反相器适于接收第一电压域中的输入信号，并且还包括由第二电压域中的电压驱动的至少一个附加晶体管。 第二反相器与第一反相器串联耦合并且可操作以在第二电压域中产生输出信号。 第二反相器包括一对相反导电类型的晶体管，并且还包括由第一电压域中的电压驱动的至少一个附加晶体管。 附加晶体管可操作以近似均衡由第一和第二逆变器产生的输出信号的下降时间。