公开(公告)号：US20190384347A1

公开(公告)日：2019-12-19

申请号：US16437705

申请日：2019-06-11

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F1/02 ,  H03K3/80 ,  H03K4/02

Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.

公开(公告)号：US20230266387A1

公开(公告)日：2023-08-24

申请号：US18168496

申请日：2023-02-13

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh SINGH ,  Ankur BAL

IPC: G01R31/317 ,  G01R31/28

CPC classification number: G01R31/31716 ,  G01R31/2851 ,  G01R31/31725

Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serial izer without utilizing a deserializer.

公开(公告)号：US20220206987A1

公开(公告)日：2022-06-30

申请号：US17548101

申请日：2021-12-10

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F13/42 ,  G06F1/06 ,  G06F1/08

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

公开(公告)号：US20210211133A1

公开(公告)日：2021-07-08

申请号：US17131917

申请日：2020-12-23

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh SINGH ,  Ankur BAL

IPC: H03L7/08 ,  H03L7/091 ,  G06F1/04

Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

公开(公告)号：US20210133124A1

公开(公告)日：2021-05-06

申请号：US17067967

申请日：2020-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F13/16 ,  G06F7/487 ,  G06F9/30 ,  G06F17/16

Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.

公开(公告)号：US20210110852A1

公开(公告)日：2021-04-15

申请号：US17015271

申请日：2020-09-09

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH ,  Vivek TRIPATHI

IPC: G11C7/10 ,  G11C7/04 ,  G11C7/22 ,  H03M1/00 ,  H03L7/107

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.