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公开(公告)号：US10217503B2
公开(公告)日：2019-02-26
申请号：US16151388
申请日：2018-10-04
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
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公开(公告)号：US12174909B2
公开(公告)日：2024-12-24
申请号：US17373935
申请日：2021-07-13
Inventor： Francesco La Rosa , Antonino Conte
Abstract: In an embodiment a method programming floating gate transistors belonging to non-volatile memory cells to multilevel threshold voltages respectively corresponding to the weight factors, performing a sensing operation of the programmed floating gate transistors with a control signal adapted to make the corresponding memory cells become conductive at an instant determined by a respective programmed threshold voltage, performing the convolutional computation by using the input values during an elapsed time for each memory cell to become conductive and outputting output values resulting from the convolutional computation.
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13.发明申请公开(公告)号：US20190035450A1
公开(公告)日：2019-01-31
申请号：US16151388
申请日：2018-10-04
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
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公开(公告)号：US20180005684A1
公开(公告)日：2018-01-04
申请号：US15389751
申请日：2016-12-23
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
IPC: G11C11/24
Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
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公开(公告)号：US20230087074A1
公开(公告)日：2023-03-23
申请号：US17940753
申请日：2022-09-08
Applicant: STMicroelectronics S.r.I.
Inventor： Gianbattista Lo Giudice , Antonino Conte
Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
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Patent Agency Ranking
公开(公告)号：US20240429928A1
公开(公告)日：2024-12-26
申请号：US18824653
申请日：2024-09-04
Applicant: STMicroelectronics S.r.I.
Inventor： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC: H03M1/06
Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
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公开(公告)号：US20230130268A1
公开(公告)日：2023-04-27
申请号：US17933972
申请日：2022-09-21
Applicant: STMicroelectronics S.r.I.
Inventor： Marco Ruta , Antonino Conte , Michelangelo Pisasale , Agatino Massimo Maccarrone , Francesco Tomaiuolo
Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.
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公开(公告)号：US12205651B2
公开(公告)日：2025-01-21
申请号：US17940753
申请日：2022-09-08
Applicant: STMicroelectronics S.r.I.
Inventor： Gianbattista Lo Giudice , Antonino Conte
Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
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公开(公告)号：US20230170914A1
公开(公告)日：2023-06-01
申请号：US18054333
申请日：2022-11-10
Applicant: STMicroelectronics S.r.I.
Inventor： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
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20.发明申请公开(公告)号：US20190206488A1
公开(公告)日：2019-07-04
申请号：US16222484
申请日：2018-12-17
Applicant: STMicroelectronics S.r.I.
Inventor： Antonino Conte
IPC: G11C13/00
Abstract: In an embodiment, a non-volatile memory device includes a memory array divided into a plurality of tiles, and a row decoder that includes main row decoding units associated to a respective group of tiles. The row decoded further includes local row decoding units, each associated to a respective tile for carrying out selection and biasing of corresponding word lines based on decoded address signals and biasing signals. Each local row decoding unit has logic-combination modules coupled to a set of word lines and include, for each word line, a pull-down stage for selecting a word line, and a pull-up stage. The pull-up stage is dynamically biased, alternatively, in a strong-biasing condition towards a tile-supply voltage when the word line is not selected, or in a weak-biasing condition when the word line is selected.
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